Image sensor

Patent metadata

Field	Value
Publication number	US-2025294265-A1
Application number	US-202418970387-A
Country	US
Kind code	A1
Filing date	Dec 5, 2024
Priority date	Mar 18, 2024
Publication date	Sep 18, 2025
Grant date	—

Abstract

An image sensor is provided. The image sensor includes: a pixel array with a pixel area and a dummy area; a row driver configured to sequentially output driving signals to the pixel array; a detection circuit configured to receive a row output signals generated based on the driving signals from the dummy area, and receive the driving signals; and a timing controller configured to provide the driving signals to the row driver, and the driving signals and a clock signal to the detection circuit. The detection circuit is further configured to identify difference values between delay times corresponding to adjacent rows of the rows, determine whether the rows are defective by comparing the difference values with a reference value, and output result values indicating whether the rows are defective.

First claim

What is claimed is:

1 . An image sensor comprising:
a pixel array comprising a pixel area and a dummy area adjacent to and on a same plane as the pixel area, the pixel area comprising pixels provided in a plurality of rows; a row driver configured to sequentially output driving signals to the pixel array; a detection circuit configured to receive a plurality of row output signals generated based on the driving signals from the dummy area, and receive the driving signals; and a timing controller configured to provide the driving signals to the row driver, and the driving signals and a clock signal to the detection circuit, wherein the detection circuit is further configured to identify difference values between delay times corresponding to adjacent rows of the plurality of rows, determine whether the plurality of rows are defective by comparing the difference values with a reference value, and output result values indicating whether the plurality of rows are defective.

2 . The image sensor of claim 1 , wherein a second output signal, from among the plurality of row output signals, first toggles from a logic low level to a logic high level in a delay time.

3 . The image sensor of claim 1 , wherein the dummy area is disposed on a first side of the pixel area, and
wherein the row driver is disposed on a second side of the pixel area opposite to the first side.

4 . The image sensor of claim 1 , wherein the plurality of rows comprises a first row and a second row, and
wherein the detection circuit is configured to: select a second row output signal from among the plurality of row output signals, generate a second count result value corresponding to the second row by counting cycles of the clock signal corresponding to a delay time of the second row output signal based on the driving signals, generate a second difference value between the second count result value and a first count result value corresponding to the first row, and determine whether the second row is defective by comparing the second difference value with the reference value.

5 . The image sensor of claim 4 , wherein the detection circuit comprises:
a signal selection circuit configured to select the second row output signal from among the plurality of row output signals; a counter circuit configured to generate the second count result value by counting cycles of the clock signal in a time interval of the second row output signal; a difference circuit configured to generate the second difference value that is a difference value between the second count result value and the first count result value; and a comparison circuit configured to output a result value according to a result of comparing the second difference value with the reference value.

6 . The image sensor of claim 5 , wherein the image sensor is configured to output the result value corresponding to a fail based on the second difference value being greater than the reference value.

7 . The image sensor of claim 5 , wherein the signal selection circuit comprises a multiplexer, and
wherein the multiplexer is configured to receive the plurality of row output signals and select the second row output signal.

8 . The image sensor of claim 5 , wherein the counter circuit is configured to:
receive the clock signal, the driving signals and the second row output signal, and generate the second count result value by counting cycles of the clock signal corresponding to a time when the second row output signal is delayed compared to the driving signals.

9 . The image sensor of claim 5 , further comprising a register configured to store the second count result value generated by the counter circuit,
wherein the difference circuit is configured to receive the first count result value and the second count result value output from the register, and generate the second difference value which is an absolute value of a difference between the first count result value and the second count result value.

10 . The image sensor of claim 5 , wherein the comparison circuit is further configured to receive the second difference value and the reference value, and determine whether the second difference value is greater than the reference value, and
wherein the reference value is one of a value input from outside or a value stored in the comparison circuit.

11 . The image sensor of claim 1 , wherein the pixel array is provided in a first semiconductor layer, and
wherein the row driver, the detection circuit, and the timing controller are provided in a second semiconductor layer located below the first semiconductor layer.

12 . An image sensor comprising:
a pixel array comprising a pixel area and a dummy area, the pixel area comprising a plurality of pixels; a row driver configured to output a driving signal to the pixel array; and a detection circuit configured to receive a plurality of row output signals from the dummy area, and receive the driving signal and a clock signal, wherein the detection circuit comprises:
a signal selection circuit configured to select an Nth row output signal from among the plurality of row output signals;
a counter circuit configured to generate an Nth count result value by counting cycles of the clock signal during a time interval of the Nth row output signal based on the driving signal;
a difference circuit configured to generate an Nth difference value between the Nth count result value and an (N−1)th count result value; and
a comparison circuit configured to detect a defect of the Nth row output signal by comparing the Nth difference value with a reference value, and
wherein the time interval comprises a delay interval in which the Nth row output signal is delayed based on the driving signal.

13 . The image sensor of claim 12 , wherein, in the pixel array,
the pixel area and the dummy area are provided on a same plane, the dummy area is provided in a second direction of the pixel area, and the row driver is provided in a direction opposite to the second direction of the pixel area.

14 . The image sensor of claim 12 , wherein the time interval comprises a delay interval that is a difference between the driving signal received by the detection circuit and the Nth row output signal.

15 . The image sensor of claim 12 , wherein the signal selection circuit comprises a multiplexer, and
wherein the multiplexer is configured to receive the plurality of row output signals and select the Nth row output signal from among the plurality of row output signals.

16 . The image sensor of claim 12 , wherein the detection circuit further comprises a register configured to store the Nth count result value generated by the counter circuit, and
wherein the difference circuit is configured to receive the (N−1)th count result value output from the register and the Nth count result value generated by the counter circuit, and generate the Nth difference value which is an absolute value of a difference between the (N−1)th count result value and the Nth count result value.

17 . The image sensor of claim 12 , wherein the comparison circuit is further configured to:
receive the Nth difference value and the reference value, compare the Nth difference value with the reference value, output the result value corresponding to a pass based on the Nth difference value being less than the reference value, and output the result value corresponding to a fail based on the Nth difference value being greater than the reference value.

18 . A method of operating an image sensor, the

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Kyungmin
• Chun Chanho
• Keel Minsun

Classifications

• H04N25/68 Primary

  applied to defects · CPC title

• H04N25/79

  Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors · CPC title

• H04N25/745

  Circuitry for generating timing or clock signals · CPC title

• H04N25/7795

  Circuitry for generating timing or clock signals · CPC title

• H04N25/76

  Addressed sensors, e.g. MOS or CMOS sensors · CPC title