Manufacturing method for semiconductor device and semiconductor wafers

Patent metadata

Field	Value
Publication number	US-2025293100-A1
Application number	US-202519225869-A
Country	US
Kind code	A1
Filing date	Jun 2, 2025
Priority date	Sep 17, 2021
Publication date	Sep 18, 2025
Grant date	—

Abstract

A method of manufacturing a semiconductor device capable of detecting occurrence of a Hi-K disappearance is provided. The method of manufacturing a semiconductor device includes a step of manufacturing a test pattern including a reference resistance, a gate leakage resistance through which a gate leakage current flows and connected in series with the reference resistance, and a step of measuring a change in voltage at a connection node between the reference resistance and the gate leakage resistance caused by the flow of the gate leakage current.

First claim

What is claimed is:

1 . A semiconductor wafer in which a plurality of semiconductor chips are disposed,
the semiconductor wafer comprising a test pattern including a reference resistance and a measurement resistance which is connected with the reference resistance in series and through which a leakage current flows, wherein a voltage at a connection node between the reference resistance and the measurement resistance is measured.

2 . The semiconductor wafer according to claim 1 wherein the test pattern is disposed on a scribe line for cutting the plurality of semiconductor chips from the semiconductor wafer.

3 . The semiconductor wafer according to claim 2 ,
wherein the measurement resistance is formed by a first semiconductor region and a first electrode disposed on the first semiconductor region through an insulating layer containing a material having a dielectric constant higher than that of a silicon nitride film, wherein the reference resistance is formed by a second semiconductor region and a second electrode disposed on the second semiconductor region through an insulating layer containing a material having a dielectric constant higher than that of the silicon nitride film.

4 . The semiconductor wafer of claim 2 ,
wherein a plurality of semiconductor chips are cut out of the semiconductor wafer after a voltage at the connection node is measured.

5 . The semiconductor wafer of claim 1 ,
wherein the measurement resistance includes a plurality of unit measurement resistances connected in parallel with each other, and wherein the test pattern includes a first logic circuit connected to the connection node.

6 . The semiconductor wafer of claim 5 ,
wherein the test pattern includes: a plurality of unit circuits; and a second logic circuit to which outputs of the plurality of unit circuits are supplied, and each of the plurality of unit circuits includes: the reference resistance; the measurement resistance; and the first logic circuit.

Assignees

• Renesas Electronics Corp

Inventors

• Amo Atsushi
• Chakihara Hiraku
• Yanagita Hiroshi
• Ono Akio

Classifications

• H10P74/207 Primary

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10P74/277 Primary

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10D64/693

  the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials · CPC title

• H10D64/685

  being perpendicular to the channel plane · CPC title

• H10D64/514

  characterised by the insulating layers · CPC title