Memory lifecycle state sensors

Patent metadata

Field	Value
Publication number	US-2025292856-A1
Application number	US-202418608355-A
Country	US
Kind code	A1
Filing date	Mar 18, 2024
Priority date	Mar 18, 2024
Publication date	Sep 18, 2025
Grant date	—

Abstract

Examples herein describe memory lifecycle state sensors. A memory lifecycle state sensor includes a memory and a processor. The processor is configured to write a first value to a cell of the memory at a first voltage, and the cell is storing a second value written to the cell at a second voltage that is greater than the first voltage. A value is read from the cell and compared with the first value. An indication of a lifecycle state for the cell is generated based on comparing the value with the first value, the first voltage, and the second voltage.

First claim

What is claimed is:

1 . A memory lifecycle state sensor comprising:
a memory; and at least one processor configured to:
write a first value to a cell of the memory at a first voltage, the cell storing a second value written to the cell at a second voltage that is greater than the first voltage;
read a value from the cell;
compare the value with the first value; and
generate an indication of a lifecycle state for the cell based on comparing the value with the first value, the first voltage, and the second voltage.

2 . The memory lifecycle state sensor of claim 1 , wherein the at least one processor is further configured to write the second value to the cell in response to the value matching the first value.

3 . The memory lifecycle state sensor of claim 1 , wherein the first value is different from the second value.

4 . The memory lifecycle state sensor of claim 1 , wherein the value is compared with the first value using cells of an additional memory.

5 . The memory lifecycle state sensor of claim 1 , wherein the at least one processor is further configured to read the second value from the cell at the first voltage.

6 . The memory lifecycle state sensor of claim 1 , wherein the at least one processor is further configured to:
write the first value to an additional cell of the memory at the first voltage, the additional cell storing the second value written to the additional cell at a third voltage; read an additional value from the additional cell; and compare the additional value with the first value.

7 . The memory lifecycle state sensor of claim 6 , wherein the third voltage is greater than the second voltage.

8 . The memory lifecycle state sensor of claim 6 , wherein the third voltage is less than the second voltage and greater than the first voltage.

9 . The memory lifecycle state sensor of claim 1 , wherein the memory includes random access memory (RAM).

10 . The memory lifecycle state sensor of claim 1 , wherein the lifecycle state is at least one of within useful life, nearing end of useful life, or end of useful life.

11 . The memory lifecycle state sensor of claim 1 , wherein the second value is written to the cell two or more times.

12 . A memory integrated circuit (IC) comprising:
a memory; and a memory lifecycle state sensor of the memory configured to:
write reference values to a cell of the memory at a first voltage;
read the reference values from the cell;
write test values to the cell at a second voltage that is less than the first voltage;
read values from the cell;
compare the values with the test values; and
generate an indication of a lifecycle state for the cell based on comparing the values with the test values.

13 . The memory IC of claim 12 , wherein values of the reference values and corresponding values of the test values are different.

14 . The memory IC of claim 12 , wherein the memory includes static random access memory (SRAM).

15 . The memory IC of claim 12 , wherein the values are compared with the test values using cells of an additional memory.

16 . The memory IC of claim 12 , wherein the memory lifecycle state sensor is further configured to write the reference values to the cell in response to the values matching the test values.

17 . A method comprising:
writing, by at least one processor, reference values to a first cell of a memory at a first voltage; writing, by the at least one processor, the reference values to a second cell of the memory at a second voltage that is less than the first voltage; writing, by the at least one processor, test values to the first cell and the second cell at a third voltage that is less than the second voltage; reading, by the at least one processor, first values from the first cell and second values from the second cell; comparing, by the at least one processor, the first values and the second values with the test values; and generating, by the at least one processor, an indication of a lifecycle state for the memory based on comparing the first values and the second values with the test values.

18 . The method of claim 17 , wherein a value of the second values does not match a corresponding value of the test values and the lifecycle state is end of useful life.

19 . The method of claim 17 , wherein the second values match corresponding values of the test values and a value of the first values does not match a corresponding value of the test values and the lifecycle state is nearing end of useful life.

20 . The method of claim 17 , wherein the first values match corresponding values of the test values and the second values match the corresponding values of the test values and the lifecycle state is within useful life.

Assignees

• Xilinx Inc

Inventors

• Anderson James
• Moore Jason J
• Wesselkamper James D
• Flateau Jr Roger D

Classifications

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C2029/0409

  Online test · CPC title

• G11C29/50016

  of retention · CPC title

• G11C29/50

  Marginal testing, e.g. race, voltage or current testing · CPC title

• G11C29/38 Primary

  Response verification devices · CPC title