Dynamic integrity verification of shaders for processing of workloads

Patent metadata

Field	Value
Publication number	US-2025292495-A1
Application number	US-202519037595-A
Country	US
Kind code	A1
Filing date	Jan 27, 2025
Priority date	Mar 12, 2024
Publication date	Sep 18, 2025
Grant date	—

Abstract

Dynamic integrity verification of shaders for processing of workloads is described. An example of an apparatus includes one or more processors including a GPU, the GPU including circuitry for dynamic verification of shaders; and a memory for storage of data, including data for one or more workloads of the GPU, the one or more processors to identify one or more shaders that can operate on protected content in the one or more workloads; transfer binary blocks of the one or more shaders to a trusted execution environment of the GPU to authenticate the one or more shaders; load hashes for the binary blocks of the one or more shaders into memory; and send a hardware command that points to a first shader of the one or more shaders for dynamic verification of the first shader.

First claim

What is claimed is:

1 . An apparatus comprising:
one or more processors including a graphics processing unit (GPU), the GPU including circuitry for dynamic verification of shaders; and a memory for storage of data, including data for one or more workloads for the GPU; wherein the one or more processors are to: identify one or more shaders that can operate on protected content in the one or more workloads; at a load time, transfer binary blocks of the one or more shaders to a trusted execution environment (TEE) of the GPU to authenticate the one or more shaders; load hashes for the binary blocks of the one or more shaders into memory; and at a run time, send a hardware command that points to a first shader of the one or more shaders for dynamic verification of the first shader.

2 . The apparatus of claim 1 , wherein the dynamic verification of the first shader includes:
fetching the first shader; determining if a computed hash of the first shader matches a hash for the first shader contained in the hashes loaded into memory; and upon determining that the hashes match, executing the first shader.

3 . The apparatus of claim 1 , wherein the load of the hashes includes loading the hashes in an isolated memory region (IMR).

4 . The apparatus of claim 1 , wherein the one or more processors are further to generate a hash of the hashes for the one or more shaders, and load the hash of hashes in a register; and
compare the hash of hashes to a computed hash of the hashes loaded in memory to confirm validity of the one or more shaders.

5 . The apparatus of claim 1 , wherein the load of the hashes includes loading one or more hashes for each of a plurality of virtual functions (VFs) in a single root input-output virtualization (SRIOV) environment.

6 . The apparatus of claim 1 , wherein an encrypted signature and write encrypted hashes for the one or more shaders are stored in a page table, the page table including an address of a clear binary for the first shader in memory.

7 . The apparatus of claim 1 , wherein the one or more shaders include, host embedded microcontroller (HuC) firmware.

8 . The apparatus of claim 1 , wherein the hashes for the binary blocks of the one or more shaders are computed offline.

9 . The apparatus of claim 1 , wherein the one or more workloads including one or more of media, three-dimensional (3D), or artificial intelligence (AI) workloads.

10 . A method comprising:
identifying one or more shaders that can operate on protected content in one or more workloads of a graphics processing unit (GPU); at a load time, transferring binary blocks of the one or more shaders to a trusted execution environment (TEE) of the GPU to authenticate the one or more shaders; loading hashes for the binary blocks of the one or more shaders into memory; and at a run time, sending a hardware command that points to a first shader of the one or more shaders for dynamic verification of the first shader.

11 . The method of claim 10 , wherein the dynamic verification of the first shader includes:
fetching the first shader; determining if a computed hash of the first shader matches a hash for the first shader contained in the hashes loaded into memory; and upon determining that the hashes match, executing the first shader.

12 . The method of claim 10 , wherein the loading of the hashes includes loading the hashes in an isolated memory region (IMR).

13 . The method of claim 10 , further comprising:
generating a hash of the hashes for the one or more shaders, and loading the hash of hashes in a register; and comparing the hash of hashes to a computed hash of the hashes loaded in memory to confirm validity of the one or more shaders.

14 . The method of claim 10 , wherein the loading of the hashes includes loading one or more hashes for each of a plurality of virtual functions (VFs) in a single root input-output virtualization (SRIOV) environment.

15 . The method of claim 10 , wherein an encrypted signature and write encrypted hashes for the one or more shaders are stored in a page table, the page table including an address of a clear binary for the first shader in memory.

16 . A graphics processor comprising:
one or more compute cores for processing of workload; and circuitry for dynamic verification of shaders; wherein the graphics processor is to: identify one or more shaders that can operate on protected content in one or more workloads of the graphics processor; at a load time, transfer binary blocks of the one or more shaders to a trusted execution environment (TEE) of the graphics processor to authenticate the one or more shaders; load hashes for the binary blocks of the one or more shaders into memory; and at a run time, send a hardware command that points to a first shader of the one or more shaders for dynamic verification of the first shader.

17 . The graphics processor of claim 16 , wherein the dynamic verification of the first shader includes:
fetching the first shader; determining if a computed hash of the first shader matches a hash for the first shader contained in the hashes loaded into memory; and upon determining that the hashes match, executing the first shader.

18 . The graphics processor of claim 16 , wherein the load of the hashes includes loading the hashes in an isolated memory region (IMR).

19 . The graphics processor of claim 16 , wherein the graphics processor is further to:
generate a hash of the hashes for the one or more shaders, and load the hash of hashes in a register; and compare the hash of hashes to a computed hash of the hashes loaded in memory to confirm validity of the one or more shaders.

20 . The graphics processor of claim 16 , wherein the load of the hashes includes loading one or more hashes for each of a plurality of virtual functions (VFs) in a single root input-output virtualization (SRIOV) environment.

Assignees

• Intel Corp

Inventors

• Kumar Gaurav
• Carreno Julien
• Embar Raghukrishnan Srinivasan
• Krishnan Vidhya
• Nemiroff Daniel

Classifications

• G06N3/09

  Supervised learning · CPC title

• G06N3/088

  Non-supervised learning, e.g. competitive learning · CPC title

• G06N3/044

  Recurrent networks, e.g. Hopfield networks · CPC title

• G06N3/0499

  Feedforward networks · CPC title

• G06N3/048

  Activation functions · CPC title