Memory system

Patent metadata

Field	Value
Publication number	US-2025285666-A1
Application number	US-202519220765-A
Country	US
Kind code	A1
Filing date	May 28, 2025
Priority date	Jul 1, 2022
Publication date	Sep 11, 2025
Grant date	—

Abstract

According to one embodiment, a memory system includes a semiconductor memory, a controller, and a first circuit. The semiconductor memory includes a nonvolatile memory cell. The controller is configured to cause the semiconductor memory to execute first and second write operations. The first write operation writes a first bit into the memory cell. The second write operation writes first data based on the first bit and a second bit into the memory cell. The first circuit checks whether or not the first bit includes a bit error. The controller is configured to cause the semiconductor memory to execute, in the second write operation, writing of the first data including the second bit and a third bit obtained by correcting the bit error of the first bit, in a case that the first bit includes the bit error.

First claim

What is claimed is:

1 . A memory system comprising:
a semiconductor memory including a memory cell configured to nonvolatilely store data having at least two bits; and a controller configured to cause the semiconductor memory to execute:
a first write operation of writing first data into the memory cell; and
a second write operation of writing second data into the memory cell, the second data having at least two bits that include a first bit and a second bit, wherein the controller is further configured to:
determine, based on an elapsed time period from execution of the first write operation, whether to receive third data read from the memory cell on which the first write operation of writing the first data has been executed, in executing the second write operation on the memory cell; and
in a case where the controller determines to receive the third data read from the memory cell,
receive the third data from the semiconductor memory;
obtain the first bit based on the third data read from the memory cell;
transfer the second bit to the semiconductor memory; and
cause the semiconductor memory to execute, in the second write operation, writing of the second data that includes the obtained first bit and the transferred second bit.

2 . The memory system according to claim 1 , wherein
the semiconductor memory further includes a data latch, wherein the controller is further configured to, in a case where the controller determines not to receive the third data read from the memory cell,
transfer the second bit to the semiconductor memory; and
cause the semiconductor memory to:
store, in the data latch, the third data read from the memory cell;
obtain the first bit based on the third data read from the memory cell and stored in the data latch; and
execute, in the second write operation, writing of the second data that includes the obtained first bit and the transferred second bit.

3 . The memory system according to claim 1 , wherein
the controller includes a first circuit configured to check whether or not the third data read from the memory cell includes a bit error, wherein the controller is further configured to, in a case where the controller determines to receive the third data read from the memory cell,
check, by using the first circuit, whether or not the third data read from the memory cell includes the bit error; and
in a case where the third data read from the memory cell includes the bit error based on a result of checking by the first circuit, obtain the first bit by correcting the bit error of the third data.

4 . The memory system according to claim 3 , wherein
the controller is further configured to, in a case where the first circuit fails to correct the bit error of the third data, cause the semiconductor memory to change a read voltage to read the third data from the memory cell.

5 . The memory system according to claim 1 , wherein
the controller is configured to determine to receive the third data read from the memory cell, in a case where the elapsed time period from the execution of the first write operation is longer than a threshold.

6 . The memory system according to claim 1 , further comprising:
a first circuit configured to check whether or not the third data read from the memory cell includes a bit error,
wherein
the controller is further configured to determine whether to execute the checking by the first circuit, in executing the second write operation on the memory cell on which the first write operation has been executed.

7 . The memory system according to claim 6 , wherein
the controller is configured to determine whether to execute the checking by the first circuit, based on the elapsed time period from the execution of the first write operation.

8 . The memory system according to claim 7 , wherein
the controller is configured to determine to execute the checking by the first circuit, in a case where the elapsed time period from the execution of the first write operation is longer than a threshold.

9 . The memory system according to claim 6 , wherein
the controller is further configured to, in a case where the first circuit fails to correct the bit error of the third data, cause the semiconductor memory to change a read voltage to read the third data from the memory cell.

10 . The memory system according to claim 1 , wherein
the memory cell is configured to nonvolatilely store the data in accordance with a threshold voltage, the first data corresponds to a first threshold voltage, and the second data, which includes the first bit and the second bit, corresponds to a second threshold voltage higher than the first threshold voltage.

11 . A method of controlling a semiconductor memory that includes a memory cell configured to nonvolatilely store data having at least two bits, the method comprising:
causing the semiconductor memory to execute a first write operation of writing first data into the memory cell; and causing the semiconductor memory to execute a second write operation of writing second data into the memory cell, the second data having at least two bits that include a first bit and a second bit, wherein the method further comprises:
determining, based on an elapsed time period from execution of the first write operation, whether to receive third data read from the memory cell on which the first write operation of writing the first data has been executed, in executing the second write operation on the memory cell.

12 . The method of according to claim 11 , further comprising:
determining to receive the third data read from the memory cell; and in response to determining to receive the third data read from the memory cell,
receiving the third data from the semiconductor memory;
obtaining the first bit based on the third data read from the memory cell;
transferring the second bit to the semiconductor memory; and
causing the semiconductor memory to execute, in the second write operation, writing of the second data that includes the obtained first bit and the transferred second bit.

13 . The method according to claim 11 , wherein
the semiconductor memory further includes a data latch, wherein the method further comprises:
determining not to receive the third data read from the memory cell; and
in response to determining not to receive the third data read from the memory cell,
transferring the second bit to the semiconductor memory;
causing the semiconductor memory to store, in the data latch, the third data read from the memory cell;
causing the semiconductor memory to obtain the first bit based on the third data read from the memory cell and stored in the data latch; and
causing the semiconductor memory to execute, in the second write operation, writing of the second data that includes the obtained first bit and the transferred second bit.

14 . The method according to claim 11 , further comprising:
managing a first circuit configured to check whether or not the third data read from the memory cell includes a bit error; determining to receive the third data read from the memory cell; and in response to determining to receive the third data read from the memory cell,
checking, by using the first circuit, whether or not the third data read from the memory cell includes the bit error;
determining that the third data read from the memory cell includes the bit error based on a result of checking by the first circuit; and
in response to determining that the third data read from the memory cell includes the bit error, obtaining the first bit by correcting the bit error of the third da

Assignees

• Kioxia Corp

Inventors

• Asami Shohei
• Kojima Yoshihisa

Classifications

• G11C7/1069

  I/O lines read out arrangements · CPC title

• G11C29/52 Primary

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C2029/0411

  Online error correction · CPC title

• G06F11/1044

  with specific ECC/EDC distribution · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title