Integrated circuit supporting physical unclonable function, system-on-chip including the same, and operation method thereof

Patent metadata

Field	Value
Publication number	US-2025279883-A1
Application number	US-202519008403-A
Country	US
Kind code	A1
Filing date	Jan 2, 2025
Priority date	Mar 4, 2024
Publication date	Sep 4, 2025
Grant date	—

Abstract

The present disclosure relates to integrated circuits including an integrated circuit supporting a physically unclonable function (PUF). An example integrated circuit includes a PUF block including a PUF cell array, and a controller configured to generate a security key based on PUF data that is generated based on the PUF block. The controller is configured to perform an error correction operation on the PUF data to generate an initial key, perform a length extension operation on the initial key to generate an intermediate key, and generate at least one of a plurality of final keys as the security key from the intermediate key.

First claim

1 . An integrated circuit configured to support a physically unclonable function (PUF), the integrated circuit comprising:
a PUF block comprising a PUF cell array; and a controller configured to generate a security key based on PUF data, the PUF data generated based on the PUF block, wherein the controller is configured to
perform an error correction operation on the PUF data, thereby generating an initial key,
perform a length extension operation on the initial key, thereby generating an intermediate key, and
generate, from the intermediate key, at least one final key of a plurality of final keys as the security key.

2 . The integrated circuit of claim 1 , wherein the error correction operation on the PUF data is based on helper data, the helper data generated in an enrollment phase and a decoding scheme, and
wherein the length extension operation on the initial key is based on the helper data and a length extension scheme.

3 . The integrated circuit of claim 2 , wherein the decoding scheme is associated with the length extension scheme.

4 . The integrated circuit of claim 1 , wherein the error correction operation on the PUF data comprises:
a bit decoding operation that masks the PUF data based on first helper data and applies a majority voting scheme to a masking result; and a block decoding operation that performs an XOR operation on a part of a result of the bit decoding operation and second helper data and applies a bose-chaudhuri-hocquenghem (BCH) decoding scheme to a remaining part of the result of the bit decoding operation.

5 . The integrated circuit of claim 4 , wherein the length extension operation on the initial key comprises:
a block encoding operation that applies a BCH encoding scheme to the initial key, performs an XOR operation on a result of the applying of the BCH encoding scheme and the second helper data, and combines the initial key with a result of the XOR operation; and a bit encoding operation that applies a repetitive scheme to a result of the block encoding operation and masks a result of applying the repetitive scheme based on the first helper data.

6 . The integrated circuit of claim 1 , wherein the PUF data comprises data output from a plurality of valid PUF cells of the PUF cell array.

7 . The integrated circuit of claim 1 , wherein a number of bits of the intermediate key matches a number of bits of the PUF data.

8 . The integrated circuit of claim 1 , wherein the at least one final key of the plurality of final keys comprises a first final key to be provided to a first security device, and wherein the controller is configured to manage the first final key to be switched from an in-use state to a discarded state based on the first final key satisfying a certain invalidity condition.

9 . The integrated circuit of claim 8 , wherein the integrated circuit comprises a one-time programmable (OTP) memory configured to store data that generates the at least one final key of the plurality of final keys, and
wherein the controller is configured to perform a program operation on the OTP memory, such that the first final key in the discarded state is not generated.

10 . The integrated circuit of claim 8 , wherein the plurality of final keys comprise a second final key, and
wherein the controller is configured to
generate the second final key instead of the first final key in the discarded state, and
provide the second final key to the first security device.

11 . (canceled)

12 . The integrated circuit of claim 1 , wherein the at least one final key of the plurality of final keys comprises a first final key, and
wherein the controller is configured to:
divide the intermediate key into N-bit units, thereby generating a plurality of sub-intermediate keys, N being an integer greater than or equal to 2; and
generate the first final key based on combining results of an XOR operation between M-bits selected from each sub-intermediate key of the plurality of sub-intermediate keys, M being an integer less than or equal to N.

13 . The integrated circuit of claim 12 , wherein the controller is configured to set, based on application information corresponding to a security device that receives the first final key, at least one of a value of N and a value of M.

14 . The integrated circuit of claim 12 , wherein the controller is configured to adjust a length of the first final key based on selectively combining some of the XOR operation results.

15 . (canceled)

16 . The integrated circuit of claim 1 , wherein the at least one final key of the plurality of final keys comprises a first final key to be provided to a first security device and a second final key to be provided to a second security device.

17 . The integrated circuit of claim 16 , wherein a number of bits of the first final key is different from a number of bits of the second final key.

18 . The integrated circuit of claim 16 , wherein the controller is configured to
perform, based on first application information corresponding to the first security device, a first setting operation, thereby generating the first final key, and perform, based on second application information corresponding to the second security device, a second setting operation, thereby generating the second final key.

19 . An operation method of an integrated circuit comprising a physically unclonable function (PUF) block, the method comprising:
receiving a first request for a first security key from a first security device; generating a first final key from a plurality of final keys based on the first request; and transmitting the first final key as the first security key to the first security device, wherein the plurality of final keys are based on an intermediate key corresponding to a result of a length extension operation on an initial key, and wherein the initial key matches a result of an error correction operation on PUF data generated based on the PUF block.

20 . The method of claim 19 , comprising:
changing the first security key from the first final key to a second final key from the plurality of final keys; receiving a second request for the first security key from the first security device; generating the second final key based on the second request; and transmitting the second final key to the first security device as the first security key.

21 - 24 . (canceled)

25 . A system-on-chip comprising:
a processor; a first security device configured to perform an encryption operation and a decryption operation on first input/output data of the processor; and an integrated circuit configured to provide a first security key to the first security device based on a physically unclonable function (PUF) block, wherein the integrated circuit is configured to
generate an initial key based on sequentially performing a bit decoding operation and a block decoding operation for error correction of PUF data, the PUF data generated through the PUF block,
generate an intermediate key based on sequentially performing a block encoding operation and a bit encoding operation on the initial key, and
generate, from the intermediate key, a first final key from a plurality of final keys as the first security key.

26 . The system-on-chip of claim 25 , comprising:
a memory controller configured to control memory operations for second input/output data of the processor; and a second security device configured to perform an encryption operation and a

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Jisu
• Kim Gapkyoung
• Lee Yongki
• Choi Hongmook

Classifications

• G06F15/7807

  System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package · CPC title

• G06F21/76

  in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• G06F21/73 Primary

  by creating or determining hardware identification, e.g. serial numbers · CPC title

• G06F11/10

  Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's · CPC title

• H04L9/14

  using a plurality of keys or algorithms · CPC title