Laser Detector Capable of Detecting a Laser Signal According to a Transient Voltage Fluctuation

Patent metadata

Field	Value
Publication number	US-2025277695-A1
Application number	US-202418628814-A
Country	US
Kind code	A1
Filing date	Apr 8, 2024
Priority date	Mar 1, 2024
Publication date	Sep 4, 2025
Grant date	—

Abstract

A laser detector includes a delay chain circuit and a warning circuit. The warning circuit is coupled to the delay chain circuit for generating a warning signal. The delay chain circuit includes N inverters coupled in series, an input terminal configured to receive an input voltage to the N inverters, and an output terminal configured to output an output voltage generated by the N inverters. N is a positive integer.

First claim

What is claimed is:

1 . A laser detector comprising:
a delay chain circuit; and a warning circuit coupled to the delay chain circuit and configured to generate a warning signal.

2 . The laser detector of claim 1 , wherein the delay chain circuit comprises:
N inverters coupled in series; an input terminal configured to receive an input voltage to the N inverters; and an output terminal configured to output an output voltage generated by the N inverters; wherein N is a positive integer.

3 . The laser detector of claim 2 , wherein after the input terminal of the delay chain circuit receives the input voltage, if at least one inverter of the N inverters of the delay chain circuit receives a laser signal, the output voltage at the output terminal of the delay chain circuit generates a transient voltage fluctuation, and the warning circuit generates the warning signal according to the transient voltage fluctuation.

4 . The laser detector of claim 2 , further comprising:
a NAND gate comprising:
a first input terminal coupled to the output terminal of the delay chain circuit;
a second input terminal configured to receive a reset signal; and
an output terminal coupled to the input terminal of the delay chain circuit.

5 . The laser detector of claim 4 , wherein if at least one inverter of the N inverters of the delay chain circuit receives a laser signal, a transient voltage fluctuation is generated at the output terminal of the NAND gate, and the warning circuit generates the warning signal according to the transient voltage fluctuation.

6 . The laser detector of claim 4 , wherein the NAND gate further comprises:
a third transistor comprising:
a first terminal configured to receive a working voltage;
a second terminal; and
a control terminal configured to receive the reset signal;
a fourth transistor comprising:
a first terminal configured to receive the working voltage;
a second terminal coupled to the second terminal of the third transistor; and
a control terminal coupled to the output terminal of the delay chain circuit;
a fifth transistor comprising:
a first terminal coupled to the input terminal of the delay chain circuit;
a second terminal; and
a control terminal coupled to the control terminal of the third transistor; and
a sixth transistor comprising:
a first terminal coupled to the second terminal of the fifth transistor;
a second terminal coupled to the ground terminal; and
a control terminal coupled to the control terminal of the fourth transistor.

7 . The laser detector of claim 6 , wherein the third transistor and the fourth transistor are two P-type metal oxide semiconductor field effect transistors, and the fifth transistor and the sixth transistor are two N-type metal oxide semiconductor field effect transistors.

8 . The laser detector of claim 6 , wherein each inverter of the N inverters comprises:
a first transistor comprising:
a first terminal configured to receive the working voltage;
a second terminal; and
a control terminal; and
a second transistor comprising:
a first terminal coupled to the second terminal of the first transistor;
a second terminal coupled to a ground terminal; and
a control terminal coupled to the control terminal of the first transistor.

9 . The laser detector of claim 8 , wherein the first transistor of the each inverter further comprises a bulk terminal configured to receive a third substrate bias voltage, and the second transistor of the each inverter further comprises a bulk terminal configured to receive a fourth substrate bias voltage.

10 . The laser detector of claim 9 , wherein the third substrate bias voltage is used for controlling a third threshold voltage of the first transistor, and the fourth substrate bias voltage is used for controlling a fourth threshold voltage of the second transistor.

11 . The laser detector of claim 2 , wherein the N inverters of the delay chain circuit are disposed outside a standard cell, and on at least one side of the standard cell.

12 . The laser detector of claim 2 , wherein the N inverters of the delay chain circuit are partially disposed outside a standard cell, and partially embedded within the standard cell.

13 . The laser detector of claim 2 , wherein the N inverters of the delay chain circuit are embedded within a standard cell.

14 . The laser detector of claim 2 , further comprising:
at least one delay chain circuit coupled to the warning circuit.

15 . The laser detector of claim 14 , wherein the warning circuit comprises an OR gate.

16 . The laser detector of claim 15 , wherein a plurality of terminals corresponding to all delay chain circuits are distributed within at least one block of a chip.

17 . The laser detector of claim 2 , wherein each inverter of the N inverters comprises:
a first transistor comprising:
a first terminal configured to receive a working voltage;
a second terminal; and
a control terminal; and
a second transistor comprising:
a first terminal coupled to the second terminal of the first transistor;
a second terminal coupled to a ground terminal; and
a control terminal coupled to the control terminal of the first transistor.

18 . The laser detector of claim 17 , wherein the first transistor is a P-type metal oxide semiconductor field effect transistor, and the second transistor is an N-type metal oxide semiconductor field effect transistor.

19 . The laser detector of claim 18 , wherein the first transistor of the each inverter further comprises a bulk terminal configured to receive a first substrate bias voltage, and the second transistor of the each inverter further comprises a bulk terminal configured to receive a second substrate bias voltage.

20 . The laser detector of claim 17 , wherein the first substrate bias voltage is used for controlling a first threshold voltage of the first transistor, and the second substrate bias voltage is used for controlling a second threshold voltage of the second transistor.

Assignees

• United Microelectronics Corp

Inventors

• Wu Kun-Yuan
• Hsu Chen-Hsien
• Wang Wei-Jen
• Chen Chien-Fu
• Chen Ruei-Yau
• Tsai Cheng-Yang

Classifications

• H10W42/405

  using active circuits · CPC title

• G06F21/75

  by inhibiting the analysis of circuitry or operation · CPC title

• G06F21/755

  with measures against power attack · CPC title

• G01J2001/4473

  Phototransistor · CPC title

• G01J1/44 Primary

  Electric circuits {(for command of an exposure part G03B7/02)} · CPC title