Array substrate and display panel

Patent metadata

Field	Value
Publication number	US-2025275242-A1
Application number	US-202519209690-A
Country	US
Kind code	A1
Filing date	May 15, 2025
Priority date	Jun 7, 2024
Publication date	Aug 28, 2025
Grant date	—

Abstract

The present disclosure discloses an array substrate and a display panel. The array substrate includes a first power signal transmission structure and a second power signal transmission structure. In a second area, the first power signal transmission structure includes a first structure and a second structure that are insulated from each other, the first structure and the second structure being arranged in a first direction; and the second power signal transmission structure includes a third structure, a part of the third structure located in the second area being disposed between the first structure and the second structure, and the third structure extending in a second direction to an active area, where the second direction intersects the first direction.

First claim

1 . An array substrate, comprising an active area, a first area, a bendable area, and a second area that are arranged in a second direction, and further comprising a first power signal transmission structure and a second power signal transmission structure,
wherein in the second area, the first power signal transmission structure comprises a first structure and a second structure that are insulated from each other, the first structure and the second structure being arranged in a first direction; and
the second power signal transmission structure comprises a third structure, a part of the third structure located in the second area being disposed between the first structure and the second structure, and the third structure extending in the second direction to the active area, wherein the second direction intersects the first direction.

2 . The array substrate according to claim 1 , wherein the second power signal transmission structure further comprises a fourth structure and a fifth structure, the fourth structure being disposed on a side of the first structure away from the third structure, and the fifth structure being disposed on a side of the second structure away from the third structure,
wherein the third structure, the fourth structure and the fifth structure are connected in the first area.

3 . The array substrate according to claim 2 , wherein the third structure comprises a first part and a second part, the first part of the third structure being disposed in the first area, and the second part of the third structure being disposed in the bendable area and the second area; the first part comprises a first main portion and at least one first branch portion, the first main portion extending in the first direction and being connected to the fourth structure and the fifth structure, and the first branch portion extending in the second direction to the active area;
the array substrate further comprises a third area, the third area and the active area being arranged in the first direction; the first area comprises a rounded corner area and a bezel area, the rounded corner area being disposed between the third area and the bezel area; in the bezel area, at least one of: the fourth structure and the fifth structure comprises a second main portion and at least one second branch portion; the second main portion extends in the first direction and is connected to the first main portion; the second branch portion extends in the second direction to the active area; the number of first branch portions and the number of second branch portions are equal to the number of sub-pixels in one row within the active area; the third structure, the fourth structure, and the fifth structure are connected in parallel; the active area comprises a signal transmission layer configured to provide a drive signal to at least one pixel of the active area; and at least part of the first part of the third structure is disposed in the same layer as the signal transmission layer.

4 . The array substrate according to claim 3 , wherein the signal transmission layer comprises a first signal transmission layer and a second signal transmission layer, the second signal transmission layer being disposed on a side of the first signal transmission layer close to a light exit surface; the first main portion of the third structure comprises a first conductive layer, the first conductive layer being disposed in the same layer as the first signal transmission layer or the second signal transmission layer;
the first branch portion of the third structure is disposed in the same layer as the first main portion; and the first conductive layer of the first main portion comprises a first lower layer, a first middle layer and a first upper layer that are disposed in a stack, the first lower layer, the first middle layer and the first upper layer being conductive layers.

5 . The array substrate according to claim 4 , wherein the signal transmission layer further comprises a third signal transmission layer disposed on a side of the second signal transmission layer close to the light exit surface; the first main portion further comprises a second conductive layer, the first conductive layer being connected to the second conductive layer, and the second conductive layer being disposed in the same layer as the third signal transmission layer;
the first conductive layer and the second conductive layer are connected in parallel; the first branch portion is disposed in the same layer as the third signal transmission layer; and the second conductive layer comprises a second lower layer, a second middle layer, and a second upper layer that are disposed in a stack, the second lower layer, the second middle layer and the second upper layer being conductive layers.

6 . The array substrate according to claim 4 , wherein the active area comprises an anode layer disposed on a side of the second signal transmission layer close to the light exit surface and configured to form at least one anode of the at least one pixel in the active area; the first main portion further comprises a second conductive layer, the first conductive layer being connected to the second conductive layer, and the second conductive layer being disposed in the same layer as the anode layer;
the first conductive layer and the second conductive layer are connected in parallel; and
the first branch portion is disposed in the same layer as the anode layer.

7 . The array substrate according to claim 6 , further comprising a third area, the third area and the active area being arranged in the first direction, wherein the first area comprises a rounded corner area and a bezel area, the rounded corner area being disposed between the third area and the bezel area; in the bezel area, at least one of: the fourth structure and the fifth structure comprises a third conductive layer and a fourth conductive layer that are connected in parallel, the third conductive layer being disposed in the same layer as the first signal transmission layer, and the fourth conductive layer being disposed in the same layer as the second signal transmission layer; and
at least one of: the fourth structure and the fifth structure further comprises a fifth conductive layer connected in parallel with the third conductive layer and the fourth conductive layer, the fifth conductive layer being disposed in the same layer as a third signal transmission layer or an anode layer.

8 . The array substrate according to claim 6 , wherein when the first conductive layer of the third structure is disposed in the same layer as the first signal transmission layer, the second signal transmission layer further comprises a bridging portion via which the first conductive layer of the third structure and the second conductive layer of the third structure are connected to each other.

9 . The array substrate according to claim 3 , wherein the second part of the third structure comprises a first sub-part and a second sub-part, wherein the first sub-part of the third structure is disposed in the bendable area, and the second sub-part of the third structure is disposed in the second area; the first sub-part is disposed in the same layer as part of the signal transmission layer, and the second sub-part is disposed in the same layer as the signal transmission layer;
the signal transmission layer comprises a first signal transmission layer and a second signal transmission layer, the first sub-part being disposed in the same layer as the first signal transmission layer or the second signal transmission layer; and the second sub-part comprises a sixth conductive layer and a seventh conductive layer that are connected in parallel, the sixth conductive layer being disposed in th

Assignees

• Yungu Gu’An Tech Co Ltd

Inventors

• Xia Bo
• He Guobing
• Guo Sheng
• Tian Miaomiao
• Duan Pei
• Ma Zhili

Classifications

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title

• Y02E10/549

  Organic PV cells · CPC title

• G09G2310/0202

  Addressing of scan or signal lines · CPC title

• G09G3/2092

  Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165) · CPC title