Integrated circuit device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2025267850-A1
Application number	US-202519010773-A
Country	US
Kind code	A1
Filing date	Jan 6, 2025
Priority date	Feb 16, 2024
Publication date	Aug 21, 2025
Grant date	—

Abstract

An integrated circuit device includes a substrate comprising a cell array area and at least one interface area, the cell array area including a plurality of active areas, the at least one interface area including an insulating interface structure, a gate structure extending across the plurality of active areas in a first lateral direction, the gate structure including a first metal pattern, a line pattern, and a second metal pattern, the first metal pattern including an extension portion and a landing portion, the extension portion vertically overlapping the plurality of active areas, and the landing portion vertically overlapping the insulating interface structure, the line pattern on the extension portion of the first metal pattern, and the second metal pattern between the first metal pattern and the line pattern.

First claim

What is claimed is:

1 . An integrated circuit device comprising:
a substrate comprising a cell array area and at least one interface area, the cell array area including a plurality of active areas, the at least one interface area including an insulating interface structure; a gate structure extending across the plurality of active areas in a first lateral direction, the gate structure partially extending into the insulating interface structure of the interface area,
the gate structure including a first metal pattern, a line pattern, and a second metal pattern,
the first metal pattern including an extension portion and a landing portion, the extension portion vertically overlapping the plurality of active areas, and the landing portion vertically overlapping the insulating interface structure,
the line pattern on the extension portion of the first metal pattern, and
the second metal pattern between the first metal pattern and the line pattern; and
at least one conductive contact contacting the landing portion of the first metal pattern, the at least one conductive contact being spaced apart from the second metal pattern.

2 . The integrated circuit device of claim 1 , wherein the landing portion of the first metal pattern has a length in a vertical direction greater than a length of the extension portion of the first metal pattern in the vertical direction.

3 . The integrated circuit device of claim 1 , wherein a material included in the first metal pattern is different from a material included in the second metal pattern.

4 . The integrated circuit device of claim 1 , wherein
the landing portion of the first metal pattern includes a first sidewall facing the line pattern; the first sidewall is spaced apart from the line pattern; and the second metal pattern is between the first sidewall and the line pattern.

5 . The integrated circuit device of claim 1 , wherein
the first metal pattern has a stepped structure where the extension portion is connected to the landing portion; and the second metal pattern has a shape corresponding to a surface profile of the first metal pattern.

6 . The integrated circuit device of claim 1 , wherein an upper surface of the landing portion of the first metal pattern is at a same vertical level as an uppermost surface of the second metal pattern.

7 . The integrated circuit device of claim 1 , wherein an upper surface of the line pattern is at a lower vertical level than an upper surface of the landing portion of the first metal pattern.

8 . The integrated circuit device of claim 1 , wherein the line pattern does not vertically overlap an upper surface of the landing portion of the first metal pattern.

9 . The integrated circuit device of claim 1 , wherein the line pattern is spaced apart from the at least one conductive contact.

10 . The integrated circuit device of claim 1 , wherein the second metal pattern does not contact an upper surface of the landing portion of the first metal pattern.

11 . An integrated circuit device comprising:
a substrate including a cell array area, the cell array area including a plurality of active areas; an insulating interface structure surrounding the cell array area, the insulating interface structure having a closed loop shape in a view from above; a gate structure extending across the plurality of active areas in a first lateral direction, the gate structure partially extending into the insulating interface structure; and at least one conductive contact contacting the gate structure on the insulating interface structure, the gate structure including a first metal pattern, a second metal pattern, and a line pattern,
the first metal pattern including an extension portion and a landing portion, the first metal pattern having a stepped structure where the extension portion meets the landing portion,
the extension portion vertically overlapping the plurality of active areas and extending in the first lateral direction, and
the landing portion vertically overlapping the insulating interface structure and contacting the at least one conductive contact at a higher vertical level than an upper surface of the extension portion,

the second metal pattern covering the upper surface of the extension portion and a sidewall of the landing portion, the sidewall facing the cell array area,
the line pattern spaced apart from the first metal pattern, and
the second metal pattern between the line pattern and the first metal pattern.

12 . The integrated circuit device of claim 11 , wherein
the first metal pattern has a first resistance; and the second metal pattern has a second resistance that is lower than the first resistance.

13 . The integrated circuit device of claim 11 , wherein an uppermost surface of the second metal pattern is at a lower vertical level than an upper surface of the landing portion.

14 . The integrated circuit device of claim 11 , wherein an upper surface of the line pattern is at a lower vertical level than the upper surface of the landing portion.

15 . The integrated circuit device of claim 11 , wherein the second metal pattern has a shape corresponding to a profile of the upper surface of the extension portion and a profile of the sidewall of the landing portion.

16 . The integrated circuit device of claim 11 , wherein
the at least one conductive contact is in contact with an upper surface of the landing portion; and the at least one conductive contact is spaced apart from a second metal pattern.

17 . The integrated circuit device of claim 11 , wherein
the gate structure further includes an insulating capping pattern, the insulating capping pattern covering the first metal pattern, the second metal pattern, and the line pattern; and the sidewall of the landing portion includes a portion contacting the insulating capping pattern.

18 . An integrated circuit device comprising:
a substrate including a cell array area, a peripheral circuit area, and an interface area, the cell array area including a plurality of active areas, the peripheral circuit area including at least one peripheral circuit active area, and the interface area between the cell array area and the peripheral circuit area, the interface area including an insulating interface structure; a gate structure extending across the plurality of active areas in a first lateral direction in the cell array area, the gate structure partially extending into the insulating interface structure of the interface area, the gate structure including a first metal pattern, a second metal pattern, and a line pattern,
the first metal pattern including an extension portion and a landing portion, the first metal pattern having a stepped structure where the extension portion meets the landing portion,
the extension portion vertically overlapping the plurality of active areas and extending in the first lateral direction, and
the landing portion vertically overlapping the insulating interface structure and having an upper surface at a higher vertical level than an upper surface of the extension portion,

the second metal pattern covering the upper surface of the extension portion and a sidewall of the landing portion,
the sidewall facing the cell array area,

the line pattern spaced apart from the first metal pattern, and
the second metal pattern between the line pattern and the first metal pattern; and
at least one conductive contact contacting the upper surface of the landing portion of the first metal pattern, the at least one conductive contact being spaced apa

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yoon Gyunghyun
• Park Jiho
• Ahn Junhyeok

Classifications

• H10B12/50

  Peripheral circuit region structures · CPC title

• H10B12/36

  the transistor being a FinFET · CPC title

• H10B12/315

  with the capacitor higher than a bit line · CPC title

• H10B12/488 Primary

  Word lines · CPC title

• H10B12/34 Primary

  the transistor being at least partially in a trench in the substrate · CPC title