Decision-feedback equalizer slicers for pulse amplitude modulation signaling

Patent metadata

Field	Value
Publication number	US-2025267046-A1
Application number	US-202418582161-A
Country	US
Kind code	A1
Filing date	Feb 20, 2024
Priority date	Feb 20, 2024
Publication date	Aug 21, 2025
Grant date	—

Abstract

An interface circuit includes a current summer, a pair of slicers and a pair of replica summing circuits. The current summer is configured to sum currents representative of a signaling state of an input signal in a sequence of transmission intervals. A first slicer is configured to generate a first decision based on a comparison of an output of the current summer and voltage level of a first threshold signal. A second slicer is configured to generate a second decision based on a comparison of the output of the current summer and voltage level of a second threshold signal. A first replica summing circuit is configured to generate the first threshold signal based on a common-mode signal that is representative of the common-mode voltage at the input of the current summer. A second replica summing circuit is configured to generate the second threshold signal based on the common mode signal.

First claim

What is claimed is:

1 . An interface circuit in a receiving device, comprising:
a current summer configured to sum a current representative of a signaling state of an input signal in a present transmission interval with currents representative of signaling states of the input signal captured in previous transmission intervals; a first slicer configured to generate a first decision based on a comparison of an output of the current summer and voltage level of a first threshold signal; a second slicer configured to generate a second decision based on a comparison of the output of the current summer and voltage level of a second threshold signal; a first replica summing circuit configured to generate the first threshold signal based on a common-mode signal that is representative of common-mode voltage at the input of the current summer; and a second replica summing circuit configured to generate the second threshold signal based on the common-mode signal.

2 . The interface circuit of claim 1 , wherein the input signal comprises a pulse amplitude modulation (PAM) signal.

3 . The interface circuit of claim 2 , wherein the first threshold signal has a voltage that lies within a first range of voltages bounded by a first pair of signaling levels associated with the PAM signal, and wherein the second threshold signal has a voltage that lies within a second range of voltages bounded by a second pair of signaling levels associated with the PAM signal.

4 . The interface circuit of claim 3 , wherein at least one signaling level in the first pair of signaling levels is different from both signaling levels in the second pair of signaling levels.

5 . The interface circuit of claim 1 , wherein the currents representative of signaling states of the input signal captured in previous transmission intervals are weighted using decision-feedback equalizer taps.

6 . The interface circuit of claim 1 , wherein the first threshold signal has a voltage level that is defined by an integral of current flow in the first replica summing circuit over a period of time.

7 . The interface circuit of claim 1 , wherein the second threshold signal has a voltage level that is defined by an integral of current flow in the second replica summing circuit over a period of time.

8 . A reference voltage generator, comprising:
a first replica summing circuit that is at least a partial replica of a current summer, the first replica summing circuit being configured to output a first threshold signal based on a common-mode voltage at an input of the current summer; and a second replica summing circuit that is at least a partial replica of the current summer, the second replica summing circuit being configured to output a second threshold signal based on the common-mode voltage at the input of the current summer, wherein:
the first threshold signal is provided to a first slicer that is configured to generate a first decision regarding signaling state of an input signal received by the summer based on voltage level of the first threshold signal, and
the second threshold signal is provided to a second slicer that is configured to generate a second decision regarding signaling state of an input signal received by the summer based on voltage level of the second threshold signal.

9 . The reference voltage generator of claim 8 , wherein the current summer is configured to sum currents provided by a plurality of current sources, including a first current representative of a signaling state of an input signal in a first transmission interval and one or more weighted currents representative of signaling states of the input signal captured in corresponding transmission intervals that precede the first transmission interval.

10 . The reference voltage generator of claim 9 , wherein weights used to provide the one or more weighted currents are configured for a decision-feedback equalizer (DFE).

11 . The reference voltage generator of claim 9 , wherein the first replica summing circuit and the first replica summing circuit are configured to sum unweighted currents.

12 . The reference voltage generator of claim 8 , wherein the first decision and the second decision relate to signaling state of a pulse amplitude modulation (PAM) signal.

13 . The reference voltage generator of claim 8 , wherein the voltage level of the first threshold signal is different from the voltage level of the second threshold signal.

14 . A method for receiving encoded signals, comprising:
summing a current representative of a signaling state of an input signal in a present transmission interval with currents representative of signaling states of the input signal captured in previous transmission intervals to obtain a summer output signal; generating a first decision based on a comparison of the summer output signal and a voltage level of a first threshold signal; generating a second decision based on a comparison of the summer output signal and a voltage level of a second threshold signal; generating the first threshold signal based on a common-mode signal that is representative of common-mode voltage of the input signal; and generating the second threshold signal based on the common-mode signal.

15 . The method of claim 14 , wherein the input signal comprises a pulse amplitude modulation (PAM) signal.

16 . The method of claim 15 , wherein the first threshold signal has a voltage that lies within a first range of voltages bounded by a first pair of signaling levels associated with the PAM signal, and wherein the second threshold signal has a voltage that lies within a second range of voltages bounded by a second pair of signaling levels associated with the PAM signal.

17 . The method of claim 16 , wherein at least one signaling level in the first pair of signaling levels is different from both signaling levels in the second pair of signaling levels.

18 . The method of claim 14 , wherein the currents representative of signaling states of the input signal captured in previous transmission intervals are weighted using decision-feedback equalizer taps.

19 . The method of claim 14 , wherein the first threshold signal has a voltage level that is defined by an integral of current flow over a period of time.

20 . The method of claim 14 , wherein the second threshold signal has a voltage level that is defined by an integral of current flow over a period of time.

Assignees

• Qualcomm Inc

Inventors

• Chung Younwoong
• Song Yu
• Chang Chia Heng

Classifications

• H04L25/03057 Primary

  with a recursive structure (H04L25/03031 takes precedence) · CPC title

• H04L25/0276

  Arrangements for coupling common mode signals · CPC title

• H04L25/0272

  Arrangements for coupling to multiple lines, e.g. for differential transmission · CPC title

• H04L25/061

  providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of DC offset (removal of DC offset in coupling arrangements H04L25/029, H04L25/0296) · CPC title

• H04L25/4917 Primary

  using multilevel codes · CPC title