Multilayer overhang roof for oled sub-pixel circuit

US2025261519A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2025261519-A1
Application numberUS-202519040816-A
CountryUS
Kind codeA1
Filing dateJan 29, 2025
Priority dateFeb 14, 2024
Publication dateAug 14, 2025
Grant date

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  5. First independent claim

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Abstract

Official abstract text for this publication.

Embodiments described herein relate to sub-pixel circuits and methods of forming sub-pixel circuits that may be utilized in a display such as an organic light-emitting diode (OLED) display. A method of forming a sub-pixel circuit includes depositing an anode over a substrate; depositing a pixel isolation structures (PIS) layer over the substrate; removing one or more portions of the PIS layer to form a plurality of first PIS and second PIS; planarizing the first PIS and the second PIS; depositing a first structure layer, a first metal-containing layer of a second structure layer, and a second metal-containing layer of the second structure layer over the substrate; disposing and patterning a first resist over the second structure layer; and removing portions of the second structure layer to form a second structure and portions of the first structure layer to form a first structure.

First claim

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What is claimed is: 1 . A sub-pixel, comprising: adjacent overhang structures disposed over a substrate, wherein the overhang structures define the sub-pixel and comprise: a second structure disposed over a first structure, wherein the second structure includes a second metal-containing layer disposed over a first metal-containing layer, the second structure including a bottom surface having a second width that is greater than a first width of a top surface of the first structure; an organic light emitting (OLE) material disposed between the adjacent overhang structures; and a cathode disposed over the OLE material between the adjacent overhang structures. 2 . The sub-pixel of claim 1 , wherein the first structure comprises amorphous silicon (a-Si). 3 . The sub-pixel of claim 1 , wherein: a first metal-containing material is sputtered to form the first metal-containing layer; and a second metal-containing material is sputtered to form the second metal-containing layer. 4 . The sub-pixel of claim 1 , wherein: the second metal-containing layer comprises chromium; and the first metal-containing layer comprises at least one of titanium or chromium oxide. 5 . The sub-pixel of claim 1 , wherein: the second structure includes a third metal-containing layer, wherein the first metal-containing layer is disposed over the third metal-containing layer. 6 . The sub-pixel of claim 5 , wherein: a first metal-containing material is sputtered to form the third metal-containing layer; a second metal-containing material is sputtered to form the first metal-containing layer; and the first metal-containing material is sputtered to form the second metal-containing layer. 7 . The sub-pixel of claim 5 , wherein: the third metal-containing layer comprises chromium; the first metal-containing layer comprises at least one of titanium or chromium oxide; and the second metal-containing layer comprises chromium. 8 . A sub-pixel circuit, comprising: a plurality of overhang structures disposed over a substrate, wherein adjacent overhang structures of the plurality of overhang structures define sub-pixels, each sub-pixel comprising: adjacent overhang structures, wherein each overhang structure comprises a second structure disposed over a first structure, wherein the second structure includes a second metal-containing layer disposed over a first metal-containing layer, the second structure including a bottom surface having a second width that is greater than a first width of a top surface of the first structure; an organic light emitting (OLE) material disposed between the adjacent overhang structures; and a cathode disposed over the OLE material between the adjacent overhang structures. 9 . The sub-pixel circuit of claim 8 , wherein the first structure comprises amorphous silicon (a-Si). 10 . The sub-pixel circuit of claim 8 , wherein: a first metal-containing material is sputtered to form the first metal-containing layer; and a second metal-containing material is sputtered to form the second metal-containing layer. 11 . The sub-pixel circuit of claim 8 , wherein: the second metal-containing layer comprises chromium; and the first metal-containing layer comprises at least one of titanium or chromium oxide. 12 . The sub-pixel circuit of claim 8 , wherein: the second structure includes a third metal-containing layer, wherein the first metal-containing layer is disposed over the third metal-containing layer. 13 . The sub-pixel circuit of claim 12 , wherein: a first metal-containing material is sputtered to form the third metal-containing layer; a second metal-containing material is sputtered to form the second metal-containing layer; and the first metal-containing material is sputtered to form the first metal-containing layer. 14 . The sub-pixel circuit of claim 12 , wherein: the third metal-containing layer comprises chromium; the first metal-containing layer comprises at least one of titanium or chromium oxide; and the second metal-containing layer comprises chromium. 15 . A method of forming a sub-pixel circuit, comprising: depositing an anode over a substrate; depositing a pixel isolation structure (PIS) layer over the substrate; removing one or more portions of the PIS layer to form a plurality of first PIS and second PIS; planarizing the first PIS and the second PIS; depositing a first structure layer, a first metal-containing layer of a second structure layer, and a second metal-containing layer of the second structure layer over the substrate; disposing and patterning a first resist over the second structure layer; and removing portions of the second structure layer to form a second structure and portions of the first structure layer to form a first structure. 16 . The method of claim 15 , wherein: depositing the first metal-containing layer comprises sputtering a first metal-containing material; and depositing the second metal-containing layer comprises sputtering a second metal-containing material. 17 . The method of claim 15 , wherein: the second metal-containing layer comprises chromium; and the first metal-containing layer comprises at least one of titanium or chromium oxide. 18 . The method of claim 15 , wherein: the second structure includes a third metal-containing layer, wherein the first metal-containing layer is deposited over the third metal-containing layer, and the method further comprising: depositing the third metal-containing layer over the first structure layer. 19 . The method of claim 18 , wherein: depositing the third metal-containing layer comprises sputtering a first metal-containing material; depositing the first metal-containing layer comprises sputtering a second metal-containing material; and depositing the second metal-containing layer comprises sputtering the first metal-containing material. 20 . The method of claim 18 , wherein: the third metal-containing layer comprises chromium; the first metal-containing layer comprises at least one of titanium or chromium oxide; and the second metal-containing layer comprises chromium.

Assignees

Inventors

Classifications

  • comprising red-green-blue [RGB] subpixels · CPC title

  • Manufacture or treatment · CPC title

  • H10K59/122Primary

    Pixel-defining structures or layers, e.g. banks · CPC title

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What does patent US2025261519A1 cover?
Embodiments described herein relate to sub-pixel circuits and methods of forming sub-pixel circuits that may be utilized in a display such as an organic light-emitting diode (OLED) display. A method of forming a sub-pixel circuit includes depositing an anode over a substrate; depositing a pixel isolation structures (PIS) layer over the substrate; removing one or more portions of the PIS layer t…
Who is the assignee on this patent?
Applied Materials Inc
What technology area does this patent fall under?
Primary CPC classification H10K59/122. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Aug 14 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).