Data Processing Method and Data Processing Apparatus

Patent metadata

Field	Value
Publication number	US-2025253866-A1
Application number	US-202519188817-A
Country	US
Kind code	A1
Filing date	Apr 24, 2025
Priority date	Oct 24, 2022
Publication date	Aug 7, 2025
Grant date	—

Abstract

This application discloses a data processing method. First data processing is performed on a plurality of first data streams obtained through first FEC encoding, to obtain m second data streams. Second FEC encoding has been performed for each of the second data streams, and each codeword obtained through the second FEC encoding includes N bits, where N=K+S. Second data processing is separately performed on the m second data streams to obtain m third data streams. Each of the third data streams includes at least one bit sequence, each bit sequence includes P+W bits, the P bits in each bit sequence are from the second data stream, and the W bits in each bit sequence are an added alignment marker, where P=N×b. Third data processing is performed on the m third data streams to obtain Y modulated symbol streams, where modulation has been performed for each of the modulated symbol streams.

First claim

1 . A data processing apparatus, comprising at least one processor and at least one transceiver coupled to the at least one processor, wherein the at least one processor is configured to:
perform first data processing on a first data stream obtained through first forward error correction (FEC) encoding, to obtain a second data stream; and second FEC encoding has been performed for the second data stream, and each codeword obtained through the second FEC encoding comprises N bits, wherein N=K+S, K represents a quantity of information bits, S represents a quantity of parity bits, K is an integer greater than or equal to 1, and S is an integer greater than or equal to 1; perform second data processing on the second data stream to obtain a third data stream, wherein the third data stream comprises at least one bit sequence, each bit sequence comprises P+W bits, the P bits in each bit sequence are from the second data stream, and the W bits in each bit sequence are added bits, wherein P=N×b, and b is an integer greater than or equal to 1; and perform third data processing on the third data stream to obtain Y modulated symbol streams, wherein Y is an integer greater than or equal to 1, modulation has been performed for each of the modulated symbol streams, and a value of a baud rate of each of the modulated symbol streams is an integer multiple of 156.25M.

2 . The apparatus according to claim 1 , wherein the value of the baud rate of each of the modulated symbol streams is 113.4375 Gbaud.

3 . The apparatus according to claim 1 , wherein W=1024.

4 . The apparatus according to claim 1 , wherein N=128, K=120.

5 . The apparatus according to claim 1 , wherein convolutional interleaving is performed for the second data stream before the second FEC encoding, and the convolutional interleaving comprises delaying an input data stream based on r delay lines, wherein r is an integer greater than 1; the delay lines comprise different quantities of storage units, a delay line with a smallest quantity of storage units comprises zero storage units, a difference between quantities of storage units in every two adjacent delay lines is Q, and each storage unit is for storing d bits; bits in the input data stream are sequentially input into the r delay lines based on sequence numbers of the r delay lines, d bits are input into each delay line for a single time, and d bits are output from each delay line for a single time; and r*d consecutive bits in a data stream that is output through the convolutional interleaving comprise d bits output from each delay line, wherein Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1.

6 . The apparatus according to claim 1 , wherein a rate of the first data stream is 850 Gbps,

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a is an integer greater than or equal to 1, G represents 10{circumflex over ( )}9, and M represents 10{circumflex over ( )}6.

7 . The apparatus according to claim 6 , wherein N=128, K=120, and

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8 . The apparatus according to claim 1 , wherein P=1088×W.

9 . The apparatus according to claim 8 , wherein the W bits comprise at least one frame synchronization sequence with a length of 48 bits.

10 . The apparatus according to claim 9 , wherein the frame synchronization sequence comprises two frame synchronization subsequences, a bit length of each of the frame synchronization subsequences is 24 bits, and the two frame synchronization subsequences are separated by eight bits in the alignment marker.

11 . The apparatus according to claim 10 , wherein values of 24 bits of one of the two frame synchronization subsequences comprise 0x9A, 0x4A, and 0x26, and values of 24 bits of the other of the two frame synchronization subsequences comprise 0x65, 0xB5, and 0xD9.

12 . The apparatus according to claim 1 , wherein the W bits comprise an alignment marker.

13 . The apparatus according to claim 1 , wherein the W bits comprise a padding bit and/or a status field.

14 . The apparatus according to claim 1 , wherein W is exactly divisible by N.

15 . The apparatus according to claim 1 , wherein at least one of the following operations is performed for the second data stream before the second FEC encoding: alignment marker lock, lane de-skewing, or lane reordering; and/or at least one of the following operations is further performed for each of the second data streams after the second FEC encoding: channel interleaving and scrambling.

16 . The apparatus according to claim 1 , wherein the at least one processor is configured to:
perform first data processing on a plurality of first data streams obtained through first forward error correction (FEC) encoding, to obtain m second data streams; separately perform second data processing on the m second data streams to obtain third data streams, wherein each of the third data streams comprises at least one bit sequence; and perform third data processing on m third data streams to obtain Y modulated symbol streams.

17 . The apparatus according to claim 16 , wherein the at least one processor is configured to:
separately perform second FEC encoding on each group of eight first data streams in the plurality of first data streams to obtain each group of eight encoded data streams; and perform channel interleaving on each group of eight encoded data streams to obtain one second data stream, to obtain the m second data streams.

18 . The apparatus according to claim 17 , wherein N=128, K=120, and the at least one processor is configured to:
obtain one inner codeword with a length of 128 bits from each encoded data stream in each group of eight encoded data streams, to obtain eight inner codewords in total; and obtain two bits from each of the eight inner codewords in a round-robin fashion, to obtain 1024 consecutive bits in the second data stream.

19 . A data processing apparatus, comprising at least one processor and at least one transceiver coupled to the at least one processo

Assignees

• Huawei Tech Co Ltd

Inventors

• Huang Kechao
• Ma Huixiao
• Yang Xiaoling
• Yan Zengchao
• Lin Youxi
• Huang Qinhui

Classifications

• H04L2001/0096

  Channel splitting in point-to-point links · CPC title

• H03M13/333

  Synchronisation on a multi-bit block basis, e.g. frame synchronisation · CPC title

• H03M13/19

  Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes · CPC title

• H03M13/2792

  Interleaver wherein interleaving is performed jointly with another technique such as puncturing, multiplexing or routing · CPC title

• H03M13/6561

  Parallelized implementations · CPC title