Semiconductor package

Patent metadata

Field	Value
Publication number	US-2025253285-A1
Application number	US-202418929827-A
Country	US
Kind code	A1
Filing date	Oct 29, 2024
Priority date	Feb 2, 2024
Publication date	Aug 7, 2025
Grant date	—

Abstract

A semiconductor package may include a semiconductor die stack in a stepped pattern, an encapsulation layer sealing the semiconductor die stack and including a first surface coplanar with a bottommost surface of the semiconductor die stack and a second surface opposite the first surface, the second surface having a groove, a printed circuit board on the second surface of the encapsulation layer and including a conductive pad facing the second surface of the encapsulation layer, a conductive connector filling the groove, and a bonding wire group penetrating the conductive connector in a vertical direction and connecting the semiconductor die stack to the conductive pad of the printed circuit board. A width of the conductive connector in a lateral direction may be greater than or equal to a width of the conductive pad in the lateral direction.

First claim

What is claimed is:

1 . A semiconductor package comprising:
a semiconductor die stack in a stepped pattern; an encapsulation layer sealing the semiconductor die stack and including a first surface and a second surface, the first surface being coplanar with a bottommost surface of the semiconductor die stack and the second surface being opposite the first surface, the second surface having a groove; a printed circuit board on the second surface of the encapsulation layer and including a conductive pad facing the second surface of the encapsulation layer; a conductive connector filling the groove; and a bonding wire group penetrating the conductive connector in a vertical direction and connecting the semiconductor die stack to the conductive pad of the printed circuit board, wherein a width of the conductive connector in a lateral direction is greater than or equal to a width of the conductive pad in the lateral direction.

2 . The semiconductor package of claim 1 , wherein a length of the conductive connector in the vertical direction is greater than a length of the conductive pad in the vertical direction.

3 . The semiconductor package of claim 1 , wherein
the printed circuit board further includes a photosensitive resist layer in contact with the second surface of the encapsulation layer, and the photosensitive resist layer is in contact with a portion of the conductive connector.

4 . The semiconductor package of claim 1 , wherein a melting point of the conductive connector is lower than a melting point of the bonding wire group.

5 . The semiconductor package of claim 1 , wherein
the bonding wire group includes a first bonding portion, the first bonding portion includes a first upward wire connected to at least one semiconductor die of the semiconductor die stack, an inclined wire connected to the first upward wire, and a second upward wire extending toward the conductive connector and connecting the inclined wire to the conductive connector.

6 . The semiconductor package of claim 1 , wherein
the bonding wire group includes a second bonding portion, and the second bonding portion extends in a straight line toward the conductive connector and connects at least one semiconductor die of the semiconductor die stack to the conductive connector.

7 . The semiconductor package of claim 1 , wherein
the bonding wire group includes a third bonding portion, and the third bonding portion includes a third upward wire connected to at least one semiconductor die of the semiconductor die stack, a horizontal wire connected to the third upward wire, and a fourth upward wire extending to the conductive connector and connecting the horizontal wire to the conductive connector.

8 . The semiconductor package of claim 1 , wherein a topmost surface of the semiconductor die stack is apart from the second surface of the encapsulation layer in the vertical direction.

9 . The semiconductor package of claim 1 , wherein the conductive pad overlaps the conductive connector in the vertical direction and is in contact with the conductive connector.

10 . The semiconductor package of claim 1 , wherein
the conductive connector includes a top surface in contact with the printed circuit board, a bottom surface opposite the top surface, and an inclined surface extending from the top surface to the bottom surface, the bottom surface of the conductive connector is in contact with the encapsulation layer, and the bottom surface of the conductive connector has a smaller area than the top surface of the conductive connector.

11 . A semiconductor package comprising:
a lower semiconductor die stack including a plurality of lower semiconductor dies stacked in a stepped pattern in a first horizontal direction; an upper semiconductor die stack on the lower semiconductor die stack, the upper semiconductor die stack including a plurality of upper semiconductor dies stacked on the lower semiconductor die stack in a stepped pattern in a first reverse horizontal direction opposite to the first horizontal direction; an encapsulation layer sealing the upper semiconductor die stack and the lower semiconductor die stack, the encapsulation layer including a first surface and a second surface, the first surface being coplanar with a bottommost surface of the lower semiconductor die stack and the second surface being opposite the first surface, the second surface having a plurality of grooves; a printed circuit board on the second surface of the encapsulation layer and including a plurality of conductive pads facing the second surface of the encapsulation layer; a first conductive connector, a second conductive connector, and a third conductive connector respectively filling the plurality of grooves; a first bonding wire group penetrating the first conductive connector in a vertical direction and connecting the lower semiconductor die stack to some of the plurality of conductive pads of the printed circuit board; and a second bonding wire group penetrating the second conductive connector and the third conductive connector in the vertical direction and connecting the upper semiconductor die stack to other conductive pads among the conductive pads of the printed circuit board, wherein a width of the first conductive connector, a width of the second conductive connector, and a width the third conductive connector in a lateral direction are greater than or equal to widths of each of the plurality of conductive pads in the lateral direction.

12 . The semiconductor package of claim 11 , wherein
the lower semiconductor die stack includes a first lower semiconductor die at a bottom of the lower semiconductor die stack and a second lower semiconductor die on the first lower semiconductor die in the stepped pattern of the lower semiconductor die stack, the first bonding wire group includes a first bonding portion connecting the first lower semiconductor die to one of the plurality of conductive pads and a second bonding portion connecting the second lower semiconductor die to an other one of the plurality of conductive pads, and the first bonding portion and the second bonding portion penetrate the first conductive connector and are electrically connected to each other via the first conductive connector.

13 . The semiconductor package of claim 11 , wherein
the upper semiconductor die stack includes a first upper semiconductor die in contact with the lower semiconductor die stack and a second upper semiconductor die stacked on the first upper semiconductor die in the stepped pattern of the upper semiconductor die stack, the second bonding wire group includes a third bonding portion connecting the first upper semiconductor die to one of the plurality of conductive pads and a fourth bonding portion connecting the second upper semiconductor die to an other one of the plurality of conductive pads, the third bonding portion penetrates the second conductive connector, the fourth bonding portion penetrates the third conductive connector, and the third bonding portion is not electrically connected to the fourth bonding portion.

14 . The semiconductor package of claim 11 , wherein
the first conductive connector, the second conductive connector, and the third conductive connector each protrude in the vertical direction, and a vertical level of a topmost end of each of the first conductive connector, the second conductive connector, and the third conductive connector is higher than a vertical level of the second surface of the encapsulation layer.

15 . The semiconductor package of claim 14 , wherein vertical levels of each

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Kwangyong

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W72/5434

  the connected ends being on auxiliary connecting means on bond pads, e.g. on other bond wires · CPC title

• H10W90/00 Primary

  Package configurations · CPC title