Etchant composition, method of manufacturing semiconductor device using the same, and semiconductor device

Patent metadata

Field	Value
Publication number	US-2025253162-A1
Application number	US-202418818736-A
Country	US
Kind code	A1
Filing date	Aug 29, 2024
Priority date	Feb 2, 2024
Publication date	Aug 7, 2025
Grant date	—

Abstract

A method of manufacturing a semiconductor device may include preparing a semiconductor structure; forming a slit recessed downward in a vertical direction from a top surface of the semiconductor structure, wherein a length of the slit in the vertical direction may be greater than a width of the slit in a horizontal direction; forming a conductive layer filling at least a portion of the slit, wherein the conductive layer may include titanium nitride, and a seam may be included in the conductive layer; and performing a first etching process using an etchant composition to etch the conductive layer. A conductive pattern may be formed inside the slit from the conductive layer due to the first etching process. The oxidizing agent may include periodic acid. The additive may include nitric acid, acetic acid, or a combination thereof.

First claim

What is claimed is:

1 . A method of manufacturing a semiconductor device, the method comprising:
preparing a semiconductor structure; forming a slit recessed downward in a vertical direction from a top surface of the semiconductor structure, wherein a length of the slit in the vertical direction is greater than a width of the slit in a horizontal direction; forming a conductive layer filling at least a portion of the slit, wherein the conductive layer includes titanium nitride and a seam in the conductive layer; performing a first etching process using an etchant composition to etch the conductive layer, wherein the etchant composition includes an oxidizing agent, an etching agent, an additive, and a solvent, a conductive pattern is formed inside the slit from the conductive layer due to the first etching process, and a vertical level of a top surface of the conductive pattern is lower than a vertical level of a top surface of the semiconductor structure; and performing a second etching process on the conductive pattern, wherein the oxidizing agent includes periodic acid, and the additive includes nitric acid, acetic acid, or a combination thereof.

2 . The method of claim 1 , wherein
the etching agent includes phosphoric acid, sulfuric acid, or a combination thereof, and the solvent includes water.

3 . The method of claim 2 , wherein, based on 100 parts by weight, the etchant composition comprises:
0.1 to 10 parts by weight of the oxidizing agent; 40 to 90 parts by weight of the etching agent; 0 to 1 part by weight of the additive; and 0 to 50 parts by weight of the solvent.

4 . The method of claim 1 , wherein the seam is not exposed to an outside area after the performing the first etching process.

5 . The method of claim 1 , wherein the seam is exposed to an outside area after the performing the first etching process.

6 . The method of claim 1 , wherein the seam is not exposed to an outside area after the performing the second etching process.

7 . The method of claim 6 , wherein the additive includes acetic acid.

8 . The method of claim 1 , wherein
a length of the seam in the vertical direction is greater than the width of the seam in the horizontal direction.

9 . The method of claim 1 , further comprising:
forming a capping pattern on the conductive pattern after the performing the second etching process, wherein the capping pattern includes a conductive material, an insulating material, or a combination thereof.

10 . A method of manufacturing a semiconductor device, the method comprising:
preparing a substrate; forming active patterns by patterning an upper portion of the substrate; forming a groove recessed downward in a vertical direction from a top surface of each of the active patterns, wherein a length of the groove in the vertical direction is greater than a width of the groove in a horizontal direction; sequentially forming a gate dielectric layer and a gate electrode layer in the groove, the gate electrode layer including titanium nitride and being formed on the gate dielectric layer, the gate electrode layer extending on a top surface of each of the active patterns, and the gate electrode layer including a seam in the gate electrode layer; performing a first etching process on the gate electrode layer using an etchant composition, wherein the etchant composition includes an oxidizing agent, an etching agent, an additive, and a solvent, a gate electrode pattern is formed from the gate electrode layer by the first etching process, and a vertical level of a top surface of the gate electrode pattern is lower than a vertical level of a top surface of each of the active patterns; and performing a second etching process on the gate electrode pattern.

11 . The method of claim 10 , wherein
the oxidizing agent includes periodic acid, the etching agent includes phosphoric acid, sulfuric acid, or a combination thereof, the additive includes nitric acid, acetic acid, or a combination thereof, and the solvent includes water.

12 . The method of claim 11 , wherein, based on 100 parts by weight, the etchant composition comprises:
0.1 to 10 parts by weight of the oxidizing agent; 40 to 90 parts by weight of the etching agent; 0 to 1 part by weight of the additive; and 0 to 50 parts by weight of the solvent.

13 . The method of claim 10 , wherein the additive includes acetic acid.

14 . The method of claim 10 , wherein
the forming active patterns by patterning the upper portion of the substrate includes forming trenches in the substrate to define the active patterns and forming a device isolation layer in the trenches before the forming the groove, after the forming active patterns, the forming the groove includes forming the groove is formed in the device isolation layer.

15 . The method of claim 10 , wherein the seam is not exposed to an outside area after performing the first etching process.

16 . The method of claim 10 , wherein the seam is exposed to an outside area after performing the first etching process.

17 . The method of claim 10 , wherein the seam is not exposed to an outside area after performing the second etching process.

18 . The method of claim 10 , wherein a length of the seam in the vertical direction is greater than the width of the seam in the horizontal direction.

19 . A method of manufacturing a semiconductor device, the method comprising:
preparing a substrate; forming active patterns by patterning an upper portion of the substrate; forming a groove recessed downward in a vertical direction from a top surface of each of the active patterns, wherein a length of the groove in the vertical direction is greater than a width of the groove in a first horizontal direction; sequentially forming a gate dielectric layer and a gate electrode layer in the groove, the gate electrode layer including titanium nitride and being formed on the gate dielectric layer, the gate electrode layer extending on a top surface of each of the active patterns, and the gate electrode layer including a seam in the gate electrode layer; performing a first etching process on the gate electrode layer using an etchant composition, wherein the etchant composition includes an oxidizing agent, an etching agent, an additive, and a solvent, a gate electrode pattern is formed from the gate electrode layer by the first etching process, the electrode pattern extends in a second horizontal direction crossing the first horizontal direction, and a vertical level of a top surface of the gate electrode pattern is lower than a vertical level of a top surface of each of the active patterns; performing a second etching process on the gate electrode pattern; forming a gate capping layer on the gate electrode pattern; forming line structures extending in the first horizontal direction on a top surface of the gate capping layer, wherein the line structures are spaced apart from each other in the second horizontal direction; and forming insulating fences between the line structures adjacent to each other in the second horizontal direction.

20 . The method of claim 19 , wherein
the oxidizing agent includes periodic acid, the etching agent includes phosphoric acid, sulfuric acid, or a combination thereof, the additive includes nitric acid, acetic acid, or a combination thereof, the solvent includes water, and based on 100 parts by weight, the etchant composition includes
0.1 to 10 parts by weight of the oxidizing agent,
40 to 90 parts by weig

Assignees

• Samsung Electronics Co Ltd
• Oci Co Ltd

Inventors

• Kim Sangwan
• Ro Geonmin
• Song Gayoung
• Yoo Younsug
• Oh Jungmin
• Chang Wook
• Bae Sangwon

Classifications

• H10P50/266 Primary

  by vapour etching only · CPC title

• H10P50/667 Primary

  by liquid etching only · CPC title

• H10B12/09

  with simultaneous manufacture of the peripheral circuit region and memory cells · CPC title

• H10D30/025

  of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318) · CPC title

• H01L21/32135 Primary

  Electricity · mapped topic