Display device and electronic apparatus including the same

Patent metadata

Field	Value
Publication number	US-2025252906-A1
Application number	US-202519010307-A
Country	US
Kind code	A1
Filing date	Jan 6, 2025
Priority date	Feb 5, 2024
Publication date	Aug 7, 2025
Grant date	—

Abstract

A display device includes first and second pixels disposed in a pixel row, first and second data lines connected to the first and second pixels, respectively, a data driver providing first and second data voltages to a first output line, and a demultiplexer selectively connecting the first and second data lines to the first output line. Each of the first and second pixels includes a first transistor, a second transistor, a third transistor, a first capacitor, and a light emitting element. The first data voltage is written to the first pixel through the first data line in a first period of a writing period in which a write gate signal has a turn-on voltage level, and the second data voltage is written to the second pixel through the second data line in a second period of the writing period that is after the first period.

First claim

What is claimed is:

1 . A display device, comprising:
a first pixel and a second pixel disposed in a pixel row; a first data line and a second data line connected to the first pixel and the second pixel, respectively; a data driver which provides a first data voltage and a second data voltage to a first output line; and a demultiplexer which selectively connects the first data line and the second data line to the first output line, wherein each of the first pixel and the second pixel comprises:
a first transistor including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node;
a second transistor including a gate electrode which receives a write gate signal, a first electrode connected to a corresponding data line among the first data line and the second data line, and a second electrode;
a third transistor including a gate electrode which receives a compensation gate signal, a first electrode connected to the third node, and a second electrode connected to the first node;
a first capacitor connected between the first node and the second electrode of the second transistor; and
a light emitting element which emits light corresponding to a driving current generated by the first transistor,
wherein the first data voltage is written to the first pixel through the first data line in a first period of a writing period in which the write gate signal has a turn-on voltage level, and wherein the second data voltage is written to the second pixel through the second data line in a second period of the writing period that is after the first period.

2 . The display device of claim 1 , further comprising:
a third pixel and a fourth pixel disposed in the pixel row; and a third data line and a fourth data line connected to the third pixel and the fourth pixel, respectively, wherein the data driver provides a third data voltage and a fourth data voltage to a second output line, wherein the demultiplexer selectively connects the third data line and the fourth data line to the second output line, wherein the third data voltage is written to the third pixel through the third data line in the first period, and wherein the fourth data voltage is written to the fourth pixel through the fourth data line in the second period.

3 . The display device of claim 2 , wherein the first pixel is one of a red pixel and a blue pixel,
wherein the second pixel is another one of the red pixel and the blue pixel different from the first pixel, and wherein each of the third and fourth pixels is a green pixel.

4 . The display device of claim 3 ,
wherein the first data line and the third data line are disposed between the first pixel and the third pixel, and wherein the second data line and the fourth data line are disposed between the second pixel and the fourth pixel.

5 . The display device of claim 3 , wherein the demultiplexer comprises:
a first selection transistor which connects the first data line to the first output line in response to a first selection signal; a second selection transistor which connects the second data line to the first output line in response to a second selection signal; a third selection transistor which connects the third data line to the second output line in response to the first selection signal; and a fourth selection transistor which connects the fourth data line to the second output line in response to the second selection signal.

6 . The display device of claim 3 , wherein the demultiplexer comprises:
a first selection transistor which connects the first data line to the first output line in response to a selection signal; and a second selection transistor which connects the third data line to the second output line in response to the selection signal, and wherein the second and fourth data lines are directly connected the first and second output lines, respectively.

7 . The display device of claim 2 , wherein the first pixel is one of a red pixel and a blue pixel,
wherein each of the second and fourth pixels is a green pixel, and wherein the third pixel is another one of the red pixel and the blue pixel different from the first pixel.

8 . The display device of claim 7 , wherein the demultiplexer comprises:
a first selection transistor which connects the first data line to the first output line in response to a first selection signal; a second selection transistor which connects the second data line to the first output line in response to a second selection signal; a third selection transistor which connects the third data line to the second output line in response to the first selection signal; and a fourth selection transistor which connects the fourth data line to the second output line in response to the second selection signal.

9 . The display device of claim 7 , wherein the demultiplexer comprises:
a first selection transistor which connects the first data line to the first output line in response to a selection signal; and a second selection transistor which connects the third data line to the second output line in response to the selection signal, and wherein the second and fourth data lines are directly connected the first and second output lines, respectively.

10 . The display device of claim 2 , further comprising:
a fifth pixel and a sixth pixel disposed in the pixel row; and a fifth data line and a sixth data line connected to the fifth pixel and the sixth pixel, respectively, wherein the data driver provides a fifth data voltage and a sixth data voltage to a third output line, wherein the demultiplexer selectively connects the fifth data line and the sixth data line to the third output line, wherein the fifth data voltage is written to the fifth pixel through the fifth data line in the first period, and wherein the sixth data voltage is written to the sixth pixel through the sixth data line in the second period.

11 . The display device of claim 10 , wherein each of the first and second pixels is a red pixel,
wherein each of the third and fourth pixels is a green pixel, and wherein each of the fifth and sixth pixels is a blue pixel.

12 . The display device of claim 11 , wherein the demultiplexer comprises:
a first selection transistor which connects the first data line to the first output line in response to a first selection signal; a second selection transistor which connects the second data line to the first output line in response to a second selection signal; a third selection transistor which connects the third data line to the second output line in response to the first selection signal; a fourth selection transistor which connects the fourth data line to the second output line in response to the second selection signal; a fifth selection transistor which connects the fifth data line to the third output line in response to the first selection signal; and a sixth selection transistor which connects the sixth data line to the third output line in response to the second selection signal.

13 . The display device of claim 11 , wherein the demultiplexer comprises:
a first selection transistor which connects the first data line to the first output line in response to a selection signal; a second selection transistor which connects the third data line to the second output line in response to the selection signal; and a third selection transistor which connects the fifth data line to the third output line in response to the selection signal, and wherein the second, fourth, and sixth data lines are directly connected the first, second, and third outpu

Assignees

• Samsung Display Co Ltd

Inventors

• Yang Jin-Wook
• Kim Hongsoo
• Park Sehyuk
• Lee Donggyu
• Jeon Jae-Hyeon
• Cho Eui-Myeong

Classifications

• G09G3/3233

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G2310/0275

  Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/0297

  Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns · CPC title