Memory system and method of controlling non-volatile memory

Patent metadata

Field	Value
Publication number	US-2025252044-A1
Application number	US-202418882227-A
Country	US
Kind code	A1
Filing date	Sep 11, 2024
Priority date	Feb 5, 2024
Publication date	Aug 7, 2025
Grant date	—

Abstract

According to one embodiment, a memory system comprises a non-volatile memory that includes a plurality of memory cells and a memory controller. The memory controller is configured to set a first read voltage based on a first shift value, acquire hard bit data by a first read operation using the first read voltage, set a second read voltage based on a second shift value, acquire soft bit data by a second read operation using the second read voltage, execute first error correction by using the hard bit data and the soft bit data, calculate a first log likelihood ratio (LLR) by using at least a result of the first error correction that has failed, and correct at least one of the first shift value and the second shift value based on the first LLR.

First claim

What is claimed is:

1 . A memory system comprising:
a non-volatile memory that includes a plurality of memory cells each configured to store data according to a threshold voltage; and a memory controller configured to:
set a first read voltage based on a first shift value;
acquire hard bit data from the plurality of memory cells by a first read operation using the first read voltage;
set a second read voltage based on a second shift value;
acquire soft bit data from the plurality of memory cells by a second read operation using the second read voltage;
execute first error correction on data read from the plurality of memory cells by using the hard bit data and the soft bit data;
in a case where the first error correction has failed, calculate a first log likelihood ratio (LLR) by using at least a result of the first error correction that has failed; and
correct at least one of the first shift value and the second shift value based on the first LLR.

2 . The memory system according to claim 1 , wherein
the memory controller is further configured to:
manage a plurality of sections each of which is obtained by dividing a range of the threshold voltage;
in the case where the first error correction has failed, calculate the first LLR for each of the plurality of sections; and
correct the first shift value such that the first read voltage is set between a first section and a second section, the first section is one of the plurality of sections and the first LLR having a negative value was calculated for the first section, and the second section is another one of the plurality of sections adjacent to the first section and the first LLR having a positive value was calculated for the second section.

3 . The memory system according to claim 2 , wherein
the memory controller is further configured to:
determine a third read voltage for use in the second read operation, in response to the correction of the first shift value; and
cause the non-volatile memory to execute a third read operation using the third read voltage.

4 . The memory system according to claim 3 , wherein the memory controller is further configured to, in a case where the first read voltage based on the first shift value that is corrected is lower than the first read voltage based on the first shift value before the correction, set the third read voltage to be lower than the first read voltage based on the first shift value that is corrected.

5 . The memory system according to claim 2 , wherein
the memory controller is further configured to:
replace the second read voltage for use in the second read operation with a third read voltage different from the second read voltage, in response to the correction of the first shift value; and
cause the non-volatile memory to execute a third read operation using the third read voltage.

6 . The memory system according to claim 5 , wherein the memory controller is further configured to replace the second read voltage that is higher than the first read voltage, with the third read voltage that is lower than the first read voltage.

7 . The memory system according to claim 2 , wherein
the memory controller is further configured to:
execute the second read operation using at least the second read voltage and a third read voltage different from the second read voltage;
replace the second read voltage with a fourth read voltage different from the second read voltage, in response to the correction of the first shift value; and
cause the non-volatile memory to execute a fourth read operation using at least the third read voltage and the fourth read voltage.

8 . The memory system according to claim 7 , wherein the memory controller is further configured to replace the second read voltage that is higher than the first read voltage, with the fourth read voltage that is lower than the first read voltage.

9 . The memory system according to claim 2 , wherein
the memory controller is further configured to:
for each of the plurality of sections, count the number of memory cells whose threshold voltage belongs to the each of the plurality of sections, using a result of the first error correction; and
calculate the first LLR based on a result of the counting.

10 . The memory system according to claim 1 , wherein the second read voltage is obtained by adding the second shift value to the first read voltage.

11 . The memory system according to claim 1 , wherein
the memory controller is further configured to:
manage a plurality of sections each of which is obtained by dividing a range of the threshold voltage;
in the case where the first error correction has failed, calculate the first LLR for each of the plurality of sections;
search the plurality of sections for a first section and a second section that is adjacent to the first section, an absolute value of a difference between the first LLR in the first section and the first LLR in the second section being smaller than a first determination value; and
in a case where a smaller value of an absolute value of the first LLR in the first section and an absolute value of the first LLR in the second section is smaller than a second determination value, correct the second shift value used to set the second read voltage corresponding to the first section, and correct a third shift value used to set a third read voltage corresponding to the second section, such that a range of the threshold voltage corresponding to the first section and a range of the threshold voltage corresponding to the second section are widened.

12 . The memory system according to claim 11 , wherein the memory controller is further configured to, in a case where the smaller value of the absolute values of the first LLRs in the first and second sections is equal to or larger than the second determination value, correct the second shift value and the third shift value such that the range of the threshold voltage corresponding to each of the first and second sections is narrowed.

13 . The memory system according to claim 1 , wherein
the memory controller is further configured to:
in a case where the first error correction has succeeded, calculate a second LLR by using at least a result of the first error correction that has succeeded; and
correct at least one of the first shift value and the second shift value based on the second LLR.

14 . The memory system according to claim 1 , wherein the memory controller is further configured to, in a case where second error correction different from the first error correction using the hard bit data has failed, execute the second read operation and execute the first error correction.

15 . The memory system according to claim 1 , wherein
the memory controller is further configured to:
execute the first error correction using the hard bit data, the soft bit data, and a preset third LLR; and
update the third LLR based on the first LLR.

16 . A method of controlling a non-volatile memory that includes a plurality of memory cells each configured to store data according to a threshold voltage, the method comprising:
setting a first read voltage based on a first shift value; acquiring hard bit data from the plurality of memory cells by a first read operation using the first read voltage; setting a second read voltage based on a second shift value; acquiring soft bit data from the plurality of memory cells by a second read operation using the second read voltage; executing first error correction on data read from the plurality of memory cells by using the hard bit data and the soft b

Assignees

• Kioxia Corp

Inventors

• Kiyooka Masahiro
• Kojima Yoshihisa
• Yu Dongxiao
• Hida Toshikatsu
• Suzuki Riki
• Nishikawa Suguru

Classifications

• G11C29/12005

  comprising voltage or current generators · CPC title

• G11C29/42 Primary

  using error correcting codes [ECC] or parity check · CPC title

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title