Using renamed registers to support multiple vset{i}vl{i} instructions

Patent metadata

Field	Value
Publication number	US-2025251935-A1
Application number	US-202519044204-A
Country	US
Kind code	A1
Filing date	Feb 3, 2025
Priority date	Dec 2, 2022
Publication date	Aug 7, 2025
Grant date	—

Abstract

A method for renaming architectural register, such as control and status register (CSR), is disclosed. The method includes decoding an instruction for updating CSR, updating the CSR based on a respective instruction of the one or more instructions, allocating a unique tag to the instruction in pipeline, and writing the tag into a mapping table for renaming the CSR. The tag can identify the CSR included in the instruction or the updated values of the CSR. The tag can be associated with a unique value. Moreover, the method can employ a First In, First Out (FIFO) queuing technique and virtual bits.

First claim

1 . A method for renaming architectural register, comprising:
decoding one or more instructions in a pipeline, wherein the one or more instructions update a control and status register (CSR); updating values in the CSR based on a respective instruction of the one or more instructions; allocating one or more tags to the respective instruction in the pipeline, wherein,
the one or more tags identify the CSR included in or associated with the one or more instructions or the updated values of the CSR, and
each of the one or more tags is associated with a unique value; and
writing the tags into a mapping table for renaming the CSR.

2 . The method of claim 1 , further comprising:
liberating overwritten tags from the mapping table when the respective instruction retires from the pipeline.

3 . The method of claim 1 , wherein the CSR includes a vector type register (vtype) and a vector length register (vl), and the method further comprises:
writing the values of the vtype and the vl into the mapping table as a combined entry; and updating the vtype and the vl as a combined unit.

4 . The method of claim 3 , wherein the CSR is updated by an instruction that is a vector set (vset) instruction, the vset instruction updates the vector type register (vtype) and the vector length register (vl).

5 . The method of claim 1 , further comprising:
allocating a register entry of the CSR into a first-in, first-out (FIFO) queue, wherein the allocation of the register entry is managed by an allocation pointer that points to a next entry to be allocated in the FIFO queue; and deallocating the register entry from the FIFO queue when the respective instruction retires from the pipeline, wherein deallocation of the register entry is managed by a retirement pointer that points to a next entry to be retired from the FIFO queue.

6 . The method of claim 5 , further comprising:
incrementing the retirement pointer to allocate a virtual index to a next physical entry in the FIFO queue.

7 . The method of claim 5 , further comprising:
allocating a virtual index to the FIFO queue using one or more virtual bits, wherein the virtual index maps to a physical entry of the FIFO queue.

8 . The method of claim 7 , further comprising:
determining a stall condition based on the retirement pointer and the allocated virtual index.

9 . The method of claim 1 , wherein the pipeline includes a primary pipeline and a vector pipeline.

10 . The method of claim 1 , further comprising:
mapping virtual FIFO entries to physical FIFO entries using a virtual index to manage instruction flow in the pipeline.

11 . An integrated circuit comprising:
a store buffer; and a processor configured to:
decode one or more instructions in a pipeline, wherein the one or more instructions update a control and status register (CSR);
update values in the CSR based on a respective instruction of the one or more instructions;
allocate one or more tags to the respective instruction in the pipeline, wherein:
the one or more tags identify the CSR included in or associated with the one or more instructions or the updated values of the CSR, and
each of the one or more tags is associated with a unique value;

write the tags into a mapping table for renaming the CSR; and
liberate overwritten tags from the mapping table when the respective instruction retires from the pipeline.

12 . The integrated circuit of claim 11 , wherein the CSR includes a vector type register (vtype) and a vector length register (vl), and the processor is further configured to:
write the values of the vtype and the vl into the mapping table as a combined entry; and update the vtype and the vl as a combined unit.

13 . The integrated circuit of claim 11 , wherein the CSR is updated by an instruction that is a vector set (vset) instruction, the vset instruction updates the vector type register (vtype) and the vector length register (vl).

14 . The integrated circuit of claim 11 , wherein the processor is further configured to:
allocate a register entry of the CSR into a first-in, first-out (FIFO) queue, wherein the allocation of the register entry is managed by an allocation pointer that points to a next entry to be allocated in the FIFO queue; allocate a virtual index to the FIFO queue using one or more virtual bits, wherein the virtual index maps to a physical entry of the FIFO queue; determine a stall condition based on a retirement pointer and the allocated virtual index; increment a retirement pointer to allocate a virtual index to a next physical entry in the FIFO queue; or deallocate the register entry from the FIFO queue when the respective instruction retires from the pipeline, wherein deallocation of the register entry is managed by a retirement pointer that points to a next entry to be retired from the FIFO queue.

15 . The integrated circuit of claim 11 , wherein the processor is further configured to:
map virtual FIFO entries to physical FIFO entries using a virtual index to manage instruction flow in the pipeline.

16 . A computer system comprising:
memory to store an instruction; and a processor coupled with the memory, configured to:
decode one or more instructions in a pipeline, wherein the one or more instructions update a control and status register (CSR);
update values in the CSR based on a respective instruction of the one or more instructions;
allocate one or more tags to the respective instruction in the pipeline, wherein:
the one or more tags identify the CSR included in or associated with the one or more instructions or the updated values of the CSR, and
each of the one or more tags is associated with a unique value;

write the tags into a mapping table for renaming the CSR; and
liberate overwritten tags from the mapping table when the respective instruction retires from the pipeline.

17 . The computer system of claim 16 , wherein the CSR includes a vector type register (vtype) and a vector length register (vl), and the processor is further configured to:
write the values of the vtype and the vl into the mapping table as a combined entry; and update the vtype and the vl as a combined unit.

18 . The computer system of claim 16 , wherein the CSR is updated by an instruction that is a vector set (vset) instruction, the vset instruction updates the vector type register (vtype) and the vector length register (vl).

19 . The computer system of claim 16 , wherein the processor is further configured to:
allocate a register entry of the CSR into a first-in, first-out (FIFO) queue, wherein the allocation of the register entry is managed by an allocation pointer that points to a next entry to be allocated in the FIFO queue; allocate a virtual index to the FIFO queue using one or more virtual bits, wherein the virtual index maps to a physical entry of the FIFO queue; determine a stall condition based on a retirement pointer and the allocated virtual index; increment a retirement pointer to allocate a virtual index to a next physical entry in the FIFO queue; or deallocate the register entry from the FIFO queue when the respective instruction retires from the pipeline, wherein deallocation of the register entry is managed by a retirement pointer that points to a next entry to be retired from the FIFO queue.

20 . The computer system of claim 16 , wherein the processor is further configured to:
map virtual FIFO entries to physical FIFO entries using a virtual index to manage instruction flow in the pipeline.

Assignees

• Sifive Inc

Inventors

• Smith Joshua

Classifications

• G06F9/3856

  Reordering of instructions, e.g. using queues or age tags · CPC title

• G06F9/30145 Primary

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/384

  Register renaming · CPC title

• G06F9/30101 Primary

  Special purpose registers · CPC title