Display panel and method of manufacturing the same, and display device

US2025248195A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2025248195-A1
Application numberUS-202318708701-A
CountryUS
Kind codeA1
Filing dateApr 28, 2023
Priority dateApr 28, 2023
Publication dateJul 31, 2025
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Provided is a display panel, including: a base substrate including at least one side region and a display region; pixel units in the display region; a terminal located in the side region on the base substrate; a first wire on the base substrate, having one end electrically connected to the terminal and the other end electrically connected to a pixel driving circuit; a second wire on the base substrate, having one end electrically connected to the terminal, the second wire extends in a direction from the terminal to a side edge of the base substrate. The display panel includes a first conductive layer, a first planarization layer, a second conductive layer and a second planarization layer sequentially provided on the base substrate. An orthographic projection of the terminal on the base substrate is spaced apart from orthographic projections of the first and second planarization layers on the base substrate.

First claim

Opening claim text (preview).

1 . A display panel, comprising: a base substrate comprising at least one side region and a display region, wherein the at least one side region is closer to a side edge of the base substrate than the display region; a plurality of pixel units provided in the display region and distributed in an array on the base substrate, wherein at least one pixel unit comprises a light emitting diode and a pixel driving circuit for driving the light emitting diode; a terminal provided on the base substrate and located in the side region; a first wire provided on the base substrate, wherein the first wire has one end electrically connected to the terminal and the other end electrically connected to the pixel driving circuit; and a second wire provided on the base substrate, wherein the second wire has one end electrically connected to the terminal, and the second wire extends in a direction from the terminal to the side edge of the base substrate, wherein the display panel comprises: a first conductive layer provided on the base substrate; a first planarization layer provided on a side of the first conductive layer away from the base substrate; a second conductive layer provided on a side of the first planarization layer away from the base substrate; and a second planarization layer provided on a side of the second conductive layer away from the base substrate, and an orthographic projection of the terminal on the base substrate is spaced apart from an orthographic projection of the first planarization layer on the base substrate, and the orthographic projection of the terminal on the base substrate is spaced apart from an orthographic projection of the second planarization layer on the base substrate. 2 . The display panel according to claim 1 , wherein in a region between the terminal and the light emitting diode closest to the terminal, the orthographic projection of the second planarization layer on the base substrate falls within the orthographic projection of the first planarization layer on the base substrate. 3 . The display panel according to claim 1 - or 2 , wherein the display panel further comprises a first passivation layer provided between the first planarization layer and the second conductive layer; and in a region between the terminal and the light emitting diode closest to the terminal, the orthographic projection of the first planarization layer on the base substrate falls within an orthographic projection of the first passivation layer on the base substrate. 4 . The display panel according to claim 3 , wherein the display panel further comprises a second passivation layer provided on a side of the second planarization layer away from the base substrate; and in the region between the terminal and the light emitting diode closest to the terminal, the orthographic projection of the second planarization layer on the base substrate falls within an orthographic projection of the second passivation layer on the base substrate. 5 . The display panel according to claim 4 , wherein the display panel comprises a first via hole located in the first passivation layer and a second via hole located in the second passivation layer; and an orthographic projection of the second via hole on the base substrate falls within an orthographic projection of the first via hole on the base substrate, and at least one of the orthographic projection of the first via hole on the base substrate and the orthographic projection of the second via hole on the base substrate falls within the orthographic projection of the terminal on the base substrate. 6 . The display panel according to claim 1 , wherein the terminal comprises a first terminal portion located in the first conductive layer and a second terminal portion located in the second conductive layer. 7 . The display panel according to claim 1 , wherein the display panel comprises a plurality of conductive pads located in the second conductive layer, and the light emitting diode comprises a first electrode in contact with a conductive pad and a second electrode in contact with another conductive pad; and the plurality of conductive pads comprise a first conductive pad closest to the side edge of the base substrate, a first side edge of the orthographic projection of the second planarization layer on the base substrate is closer to the terminal than a first side edge of an orthographic projection of the first conductive pad on the base substrate, the first side edge of the orthographic projection of the first conductive pad on the base substrate is a side edge facing the terminal among side edges of the orthographic projection of the first conductive pad on the base substrate, and the first side edge of the orthographic projection of the second planarization layer on the base substrate is a side edge facing the terminal among side edges of the orthographic projection of the second planarization layer on the base substrate. 8 . The display panel according to claim 7 , wherein the first side edge of the orthographic projection of the second planarization layer on the base substrate comprises a first side edge portion, and the first side edge portion of the second planarization layer is a portion of the first side edge of the second planarization layer directly opposite to the terminal; and the first side edge of the orthographic projection of the first conductive pad on the base substrate is spaced apart from the first side edge portion of the first side edge of the orthographic projection of the second planarization layer on the base substrate by a first specified distance in a first direction perpendicular to the side edge of the base substrate. 9 . The display panel according to claim 8 , wherein a first side edge of the orthographic projection of the first planarization layer on the base substrate comprises a first side edge portion, the first side edge of the orthographic projection of the first planarization layer on the base substrate is a side edge facing the terminal among side edges of the orthographic projection of the first planarization layer on the base substrate, and the first side edge portion of the first planarization layer is a portion of the first side edge of the first planarization layer directly opposite to the terminal; and the first side edge portion of the first side edge of the orthographic projection of the first planarization layer on the base substrate is closer to the terminal than the first side edge portion of the first side edge of the orthographic projection of the second planarization layer on the base substrate. 10 . The display panel according to claim 9 , wherein the first side edge portion of the first side edge of the orthographic projection of the first planarization layer on the base substrate is spaced apart from the first side edge portion of the first side edge of the orthographic projection of the second planarization layer on the base substrate by a second specified distance in the first direction. 11 . The display panel according to claim 10 , wherein the first side edge portion of the first side edge of the orthographic projection of the first planarization layer on the base substrate is spaced apart from a first side edge of the orthographic projection of the terminal on the base substrate by a third specified distance in the first direction, and the first side edge of the orthographic projection of the terminal on the base substrate is farthest away from the side edge of the base substrate in the first direction among side edges of the orthographic projection of the terminal on the base substrate. 12 . The display panel according to claim 11 , wherein the third specified distance is

Assignees

Inventors

Classifications

  • H10H29/39Primary

    Connection of the pixel electrodes to the driving transistors · CPC title

  • Interconnections, e.g. wiring lines or terminals (connection of the pixel electrodes to the driving transistors H10H29/39) · CPC title

  • characterised by their shape · CPC title

  • G09G3/32Primary

    semiconductive, e.g. using light-emitting diodes [LED] · CPC title

  • Insulating layers formed between the driving transistors and the LEDs · CPC title

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What does patent US2025248195A1 cover?
Provided is a display panel, including: a base substrate including at least one side region and a display region; pixel units in the display region; a terminal located in the side region on the base substrate; a first wire on the base substrate, having one end electrically connected to the terminal and the other end electrically connected to a pixel driving circuit; a second wire on the base su…
Who is the assignee on this patent?
Beijing Boe Technology Dev Co Ltd, Boe Technology Group Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10H29/39. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Jul 31 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).