Semiconductor device and semiconductor circuit

Patent metadata

Field	Value
Publication number	US-2025248112-A1
Application number	US-202519181444-A
Country	US
Kind code	A1
Filing date	Apr 17, 2025
Priority date	Mar 12, 2021
Publication date	Jul 31, 2025
Grant date	—

Abstract

A semiconductor device of embodiments includes: a semiconductor layer including a first trench, a second trench, a first semiconductor region of a first conductive type, a second semiconductor region of a second conductive type provided between a first face and the first semiconductor region, between the first trench and the second trench, and in contact with the second trench, a third semiconductor region of a first conductive type provided between the first trench and the second semiconductor region, a fourth semiconductor region of a second conductive type provided between the third semiconductor region and the first face, and a fifth semiconductor region of a second conductive type provided between the second semiconductor region and the first face, spaced from the fourth semiconductor region, in contact with the second trench; a first electrode on a first face side; and a second electrode on a second face side.

First claim

1 - 4 . (canceled)

5 . A semiconductor device comprising:
a semiconductor layer having a first face and a second face opposite to the first face and including:
a first trench provided in a first face side;
a second trench provided in a first face side;
a first semiconductor region of a first conductive type in contact with the first trench and the second trench;
a second semiconductor region of a second conductive type provided between the first face and the first semiconductor region, the second semiconductor region provided between the first trench and the second trench, and the second semiconductor region being in contact with the second trench;
a third semiconductor region of a first conductive type provided between the first semiconductor region and the first face, the third semiconductor region provided between the first trench and the second semiconductor region, the third semiconductor region being in contact with the first trench, and the third semiconductor region being in contact with the second semiconductor region;
a fourth semiconductor region of a second conductive type provided between the third semiconductor region and the first face, the fourth semiconductor region provided between the first trench and the second semiconductor region, the fourth semiconductor region being in contact with the first trench, the fourth semiconductor region being in contact with the second semiconductor region, and the fourth semiconductor region being having a second conductive type impurity concentration higher than a second conductive type impurity concentration in the second semiconductor region; and
a fifth semiconductor region of a second conductive type provided between the second semiconductor region and the first face, the fifth semiconductor region being in contact with the second trench, and the fifth semiconductor region being having a second conductive type impurity concentration higher than the second conductive type impurity concentration in the second semiconductor region, and the second semiconductor region being provided between the fourth semiconductor region and the fifth semiconductor region;
a first electrode provided on the first face side of the semiconductor layer and in contact with the second semiconductor region, the fourth semiconductor region, and the fifth semiconductor region; a second electrode provided on a second face side of the semiconductor layer; and a third electrode provided in the first trench and the second trench and electrically separated from the first electrode and the second electrode.

6 . The semiconductor device according to claim 5 ,
wherein, when the first conductive type is an n type, a voltage making a side of the second electrode positive is applied between the first electrode and the second electrode, and a voltage negative with respect to the first electrode is applied to the third electrode simultaneously, and when the first conductive type is a p type, a voltage making the side of the second electrode negative is applied between the first electrode and the second electrode, and a voltage positive with respect to the first electrode is applied to the third electrode simultaneously.

7 . The semiconductor device according to claim 5 , further comprising:
an electrode pad provided on the first face side of the semiconductor layer and electrically connected to the third electrode.

8 . A semiconductor device comprising:
a semiconductor layer having a first face and a second face opposite to the first face and including:
a first trench provided in a first face side;
a second trench provided in a first face side;
a first semiconductor region of a first conductive type in contact with the first trench and the second trench;
a second semiconductor region of a second conductive type provided between the first face and the first semiconductor region, the second semiconductor region provided between the first trench and the second trench, and the second semiconductor region being in contact with the second trench;
a third semiconductor region of a first conductive type provided between the first semiconductor region and the first face, the third semiconductor region provided between the first trench and the second semiconductor region, the third semiconductor region being in contact with the first trench, and the third semiconductor region being in contact with the second semiconductor region;
a fourth semiconductor region of a second conductive type provided between the third semiconductor region and the first face, the fourth semiconductor region provided between the first trench and the second semiconductor region, the fourth semiconductor region being in contact with the first trench, the fourth semiconductor region being in contact with the second semiconductor region, and the fourth semiconductor region being having a second conductive type impurity concentration higher than a second conductive type impurity concentration in the second semiconductor region; and
a fifth semiconductor region of a second conductive type provided between the second semiconductor region and the first face, the fifth semiconductor region being in contact with the second trench, and the fifth semiconductor region being having a second conductive type impurity concentration higher than the second conductive type impurity concentration in the second semiconductor region, and the second semiconductor region being provided between the fourth semiconductor region and the fifth semiconductor region;
a first electrode provided on the first face side of the semiconductor layer and in contact with the second semiconductor region, the fourth semiconductor region, and the fifth semiconductor region; a second electrode provided on a second face side of the semiconductor layer; and wherein a first portion of the first electrode makes Schottky contact with the second semiconductor region, a second portion of the first electrode makes ohmic contact with the fourth semiconductor region, and a third portion of the first electrode makes ohmic contact with the fifth semiconductor region.

9 . A semiconductor circuit, comprising:
the semiconductor device according to claim 5 ; and a control circuit driving the semiconductor device, the control circuit applying a voltage making a side of the second electrode positive is applied between the first electrode and the second electrode, and a voltage negative with respect to the first electrode is applied to the third electrode simultaneously, when the first conductive type is an n type, and the control circuit applying a voltage making the side of the second electrode negative is applied between the first electrode and the second electrode, and a voltage positive with respect to the first electrode is applied to the third electrode simultaneously, when the first conductive type is a p type.

10 . A semiconductor circuit, comprising:
the semiconductor device according to claim 6 ; and a control circuit driving the semiconductor device, the control circuit applying a voltage making a side of the second electrode positive is applied between the first electrode and the second electrode, and a voltage negative with respect to the first electrode is applied to the third electrode simultaneously, when the first conductive type is an n type, and the control circuit applying a voltage making the side of the second electrode negative is applied between the first electrode and the second electrode, and a voltage positive with respect to the first electrode is applied to the third electrode simultaneously, when the first conductive type is a p type.

11 . A semiconductor circuit, comprising:
the semiconductor device according to claim 7 ; and a control circuit driving the semiconduc

Assignees

• Toshiba Kk
• Toshiba Electronic Devices & Storage Corp
• Toshiba Electronics Devices & Storage Corp

Inventors

• Matsudai Tomoko
• Iwakaji Yoko
• Itokazu Hiroko

Classifications

• H10D62/109

  Reduced surface field [RESURF] PN junction structures · CPC title

• H10D12/481

  having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs · CPC title

• H10D8/50

  PIN diodes · CPC title

• H03K17/08128

  in composite switches · CPC title

• H10D62/129

  Cathode regions of diodes · CPC title