Semiconductor package

Patent metadata

Field	Value
Publication number	US-2025246573-A1
Application number	US-202419002303-A
Country	US
Kind code	A1
Filing date	Dec 26, 2024
Priority date	Jan 31, 2024
Publication date	Jul 31, 2025
Grant date	—

Abstract

A semiconductor package includes a package substrate including substrate pads on an upper portion of the package substrate, a first semiconductor chip on the package substrate, a first chip pad on the first semiconductor chip, a first conductive connection pattern on an upper surface of the first chip pad, an upper surface of the first semiconductor chip, and an upper surface of a first substrate pad among the substrate pads, and a first insulation layer on the package substrate and covering the first semiconductor chip, the first chip pad and the first conductive connection pattern.

First claim

What is claimed is:

1 . A semiconductor package comprising:
a package substrate including substrate pads on an upper portion of the package substrate; a first semiconductor chip on the package substrate; a first chip pad on the first semiconductor chip; a first conductive connection pattern on an upper surface of the first chip pad, an upper surface of the first semiconductor chip, and an upper surface of a first substrate pad among the substrate pads; and a first insulation layer on the package substrate, the first insulation layer covering the first semiconductor chip, the first chip pad and the first conductive connection pattern.

2 . The semiconductor package according to claim 1 , further comprising:
a first chip protective layer on the first semiconductor chip, the first chip protective layer covering a sidewall of the first chip pad, wherein the first insulation layer covers the first chip protection layer.

3 . The semiconductor package according to claim 2 , wherein
the first conductive connection pattern has a shape of a line extending in a horizontal direction on an upper surface of the first chip protective layer and the upper surface of the first chip pad and a shape of a line extending in a vertical direction on a sidewall of the first chip protective layer and the sidewall of the first semiconductor chip, and the first conductive connection pattern is bent at an interface between the upper surface and the sidewall of the first chip protective layer.

4 . The semiconductor package according to claim 1 , wherein the first conductive connection pattern includes gold, silver or copper.

5 . The semiconductor package according to claim 1 , wherein the first insulation layer includes a thermosetting resin.

6 . The semiconductor package according to claim 1 , wherein the first insulation layer includes an inorganic insulation material.

7 . The semiconductor package according to claim 1 , further comprising:
a second semiconductor chip on the first insulation layer; a second chip pad on the second semiconductor chip; a second conductive connection pattern on an upper surface of the second chip pad, a sidewall of the second semiconductor chip, an upper surface and a sidewall of the first insulation layer, and an upper surface of a second substrate pad among the substrate pads; and a second insulation layer on the package substrate, the second insulation layer covering the first insulation layer, the second semiconductor chip, the second chip pad, and the second conductive connection pattern.

8 . The semiconductor package according to claim 7 , further comprising:
a second chip protective layer on the second semiconductor chip, the second chip protective layer covering a sidewall of the second chip pad, wherein the second insulation layer covers the second chip protection layer.

9 . The semiconductor package according to claim 8 , wherein
the second conductive connection pattern has a shape of a line extending in a horizontal direction on an upper surface of the second chip protective layer and the upper surface of the second chip pad, a shape of a line extending in a vertical direction on a sidewall of the second chip protective layer and the sidewall of the second semiconductor chip, a shape of a line extending in the horizontal direction on the upper surface of the first insulation layer, and a shape of a line extending in the vertical direction on the sidewall of the first insulation layer, and the second conductive connection pattern is bent at an interface between the upper surface and the sidewall of the second chip protective layer, at an interface between the sidewall of the second semiconductor chip and the upper surface of the first insulation layer, and at an interface between the upper surface and the sidewall of the first insulation layer.

10 . The semiconductor package according to claim 7 , further comprising:
an adhesion layer between the upper surface of the first insulation layer and a lower surface of the second semiconductor chip.

11 . The semiconductor package according to claim 7 , further comprising:
a third semiconductor chip on the second insulation layer; a third chip pad on the third semiconductor chip; and a third conductive connection pattern on an upper surface of the third chip pad, a sidewall of the third semiconductor chip, an upper surface and a sidewall of the second insulation layer, and an upper surface of a third substrate pad among the substrate pads.

12 . The semiconductor package according to claim 11 , further comprising:
a third chip protective layer on the third semiconductor chip, the third chip protective layer covering a sidewall of the third chip pad, wherein the third conductive connection pattern covers the third chip protection layer.

13 . The semiconductor package according to claim 12 , wherein
the third conductive connection pattern has a shape of a line extending in a horizontal direction on an upper surface of the third chip protective layer and the upper surface of the third chip pad, a shape of a line extending in a vertical direction on a sidewall of the third chip protective layer and the sidewall of the third semiconductor chip, a shape of a line extending in the horizontal direction on the upper surface of the second insulation layer, and a shape of a line extending in the vertical direction on the sidewall of the second insulation layer, and the third conductive connection pattern is bent at an interface between the upper surface and the sidewall of the third chip protective layer, at an interface between the sidewall of the third semiconductor chip and the upper surface of the second insulation layer, and at an interface between the upper surface and the sidewall of the second insulation layer.

14 . The semiconductor package according to claim 7 , further comprising:
a third semiconductor chip on the second insulation layer; a third chip pad on the third semiconductor chip; a third chip protective layer on the third semiconductor chip, the third chip protective layer covering a sidewall of the third chip pad; and a third conductive connection pattern on an upper surface and a sidewall of the third chip protective layer, a sidewall of the third semiconductor chip and an upper surface of the second insulation layer, the third conductive connection pattern extending through the second insulation layer and contacting the second conductive connection pattern.

15 . A semiconductor package comprising:
a package substrate including substrate pads on an upper portion of the package substrate; semiconductor chips stacked on the package substrate; chip pads on the semiconductor chips, respectively; and a conductive connection pattern on an upper surface of each of the chip pads, a sidewall of a corresponding one of the semiconductor chips, and a respective one of the substrate pads.

16 . A semiconductor package comprising:
a package substrate including first, second, and third substrate pads on an upper portion of the package substrate; a first semiconductor chip on the package substrate; a first chip pad on the first semiconductor chip; a first chip protective layer on the first semiconductor chip, the first chip protective layer covering a sidewall of the first chip pad; a first conductive connection pattern on an upper surface of the first chip pad, an upper surface and a sidewall of the first chip protective layer, a sidewall of the first semiconductor chip, and an upper surface of a first substrate pad; a first insulation layer on the package substr

Assignees

• Samsung Electronics Co Ltd

Inventors

• Seo Wonil
• Lee Kwangyong
• Shin Jiwon
• Lee Sanghyeon

Classifications

• H10W72/552

  comprising metals or metalloids, e.g. silver · CPC title

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/531

  Shapes of wire connectors · CPC title

• H10W72/07553

  changes in shapes · CPC title