Chip package and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-2025246530-A1
Application number	US-202519015618-A
Country	US
Kind code	A1
Filing date	Jan 9, 2025
Priority date	Jan 31, 2024
Publication date	Jul 31, 2025
Grant date	—

Abstract

A chip package includes a mother chip, a daughter chip, a molding compound, a first redistribution layer, and a second redistribution layer. The daughter chip is located on a first surface of the mother chip. The molding compound covers the mother chip and the daughter chip, and the daughter chip is surrounded by the molding compound. The first redistribution layer is located on the first surface of the mother chip and is covered by the molding compound. The second redistribution layer is electrically connected to the first redistribution layer, and is located on one of a second surface of the mother chip and a surface of the molding compound. One of the first redistribution layer and the second redistribution layer is electrically connected to the daughter chip, and the other is electrically connected to the mother chip.

First claim

What is claimed is:

1 . A chip package, comprising:
a mother chip; a daughter chip located on a first surface of the mother chip; a molding compound covering the mother chip and the daughter chip, wherein the daughter chip is surrounded by the molding compound; a first redistribution layer located on the first surface of the mother chip and covered by the molding compound; and a second redistribution layer electrically connected to the first redistribution layer and located on one of a second surface of the mother chip opposite to the first surface and a surface of the molding compound that faces away from the mother chip and the daughter chip, wherein one of the first redistribution layer and the second redistribution layer is electrically connected to the daughter chip, and the other of the first redistribution layer and the second redistribution layer is electrically connected to the mother chip.

2 . The chip package of claim 1 , wherein the daughter chip has a micro bump located on the first surface of the mother chip and electrically connected to the first redistribution layer.

3 . The chip package of claim 2 , further comprising:
an underfill layer located between the daughter chip and the mother chip and surrounding the micro bump.

4 . The chip package of claim 3 , further comprising:
a passivation layer located between the underfill layer and the mother chip.

5 . The chip package of claim 1 , further comprising:
a conductive pillar located on the first redistribution layer and surrounded by the molding compound, wherein two ends of the conductive pillar are respectively in electrical contact with the first redistribution layer and the second redistribution layer.

6 . The chip package of claim 1 , further comprising:
a conductive pillar located on a surface of the daughter chip facing away from the mother chip, and electrically connected to the second redistribution layer and surrounded by the molding compound.

7 . The chip package of claim 1 , wherein the mother chip has a through hole and a conductive pad in the through hole, and the second redistribution layer extends into the through hole and is in electrical contact with the conductive pad.

8 . The chip package of claim 7 , wherein the through hole is tapered from the second surface of the mother chip to the conductive pad.

9 . The chip package of claim 7 , wherein the through hole is tapered from the first surface of the mother chip to the conductive pad.

10 . The chip package of claim 1 , further comprising:
a die attach film located between the daughter chip and the mother chip.

11 . The chip package of claim 10 , further comprising:
a passivation layer located between the die attach film and the mother chip.

12 . The chip package of claim 1 , further comprising:
a first passivation layer located on the second redistribution layer and the second surface of the mother chip.

13 . The chip package of claim 12 , further comprising:
a conductive structure located on the second redistribution layer and in the first passivation layer.

14 . The chip package of claim 12 , further comprising:
a second passivation layer located between the second redistribution layer and the first passivation layer.

15 . The chip package of claim 1 , further comprising:
a first passivation layer located on the second redistribution layer and the surface of the molding compound that faces away from the mother chip and the daughter chip.

16 . The chip package of claim 15 , further comprising:
a conductive structure located on the second redistribution layer and in the first passivation layer.

17 . The chip package of claim 16 , further comprising:
a second passivation layer located between the second redistribution layer and the surface of the molding compound.

18 . The chip package of claim 1 , wherein the second surface of the mother chip has an image sensing region.

19 . The chip package of claim 1 , further comprising:
a micro bump located on the second surface of the mother chip.

20 . A manufacturing method of a chip package, comprising:
forming a first redistribution layer on a first surface of a mother chip; disposing a daughter chip on the first surface of the mother chip; forming a molding compound covering the mother chip and the daughter chip, wherein the daughter chip is surrounded by the molding compound, and the first redistribution layer is covered by the molding compound; and forming a second redistribution layer electrically connected to the first redistribution layer and on one of a second surface of the mother chip opposite to the first surface and a surface of the molding compound that faces away from the mother chip and the daughter chip, wherein one of the first redistribution layer and the second redistribution layer is electrically connected to the daughter chip, and the other of the first redistribution layer and the second redistribution layer is electrically connected to the mother chip.

Assignees

• Xintec Inc

Inventors

• Suen Wei-Luen
• Chen Po-Jung
• Cheng Chia Ming
• Lin Po-Shen
• Lai Jiun-Yen
• Liu Tsang-Yu

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title