Apparatuses and methods for storing and writing multiple parameter codes for memory operating parameters

Patent metadata

Field	Value
Publication number	US-2025246216-A1
Application number	US-202519183136-A
Country	US
Kind code	A1
Filing date	Apr 18, 2025
Priority date	Apr 7, 2014
Publication date	Jul 31, 2025
Grant date	—

Abstract

Apparatuses and methods for writing and storing parameter codes for operating parameters, and selecting between the parameter codes to set an operating condition for a memory are disclosed. An example apparatus includes a first mode register and a second mode register. The first mode register is configured to store first and second parameter codes for a same operating parameter. The second mode register is configured to store a parameter code for a control parameter to select between the first and second parameter codes to set a current operating condition for the operating parameter. An example method includes storing in a first register a first parameter code for an operating parameter used to set a first memory operating condition, and further includes storing in a second register a second parameter code for the operating parameter used to set a second memory operating condition.

First claim

What is claimed is:

1 . An apparatus comprising:
a memory controller configured to write a first parameter code and a second parameter code for an operating parameter in a mode register of a memory device and further configured to write a third parameter code for a control parameter to set a current operation condition of the memory device to one of a plurality of operating conditions.

2 . The apparatus of claim 1 , wherein the memory controller is configured to perform training operations for the plurality off operating conditions to determine the first and second parameter codes for the operating parameter.

3 . The apparatus of claim 1 , wherein the plurality of operating conditions are related to operating conditions for a command bus coupled to the memory device and the memory controller.

4 . The apparatus of claim 1 , wherein the memory controller is configured to provide a mode register write command to cause the first, second, or third parameter code to be written to the mode register.

5 . The apparatus of claim 1 , wherein the operating parameter comprises at least one of a burst length operating parameter, a preamble operating parameter, or a precharge operating parameter.

6 . The apparatus of claim 1 , wherein the operating parameter comprises at least one of a postamble operating parameter, a latency parameter, or a drive strength parameter.

7 . The apparatus of claim 1 , wherein the operating parameter comprises at least one of a data bus interface operating parameter, an on-die termination operating parameter, or a voltage reference operating parameter.

8 . An apparatus comprising:
a memory controller configured to write a value to a mode register of a memory device to cause the memory device to switch between a plurality of set points based on the value written to the mode register.

9 . The apparatus of claim 8 , wherein writing the value to the mode register further causes the memory device to switch a plurality of operating parameters associated with the plurality of set points simultaneously.

10 . The apparatus of claim 8 , wherein set points of the plurality of set points are associated with different operating frequencies of the memory device.

11 . The apparatus of claim 8 , wherein the memory controller is configured to write a second value to the mode register to determine which register of a plurality of registers of the mode register a third value is written to.

12 . The apparatus of claim 11 , wherein the third value comprises an operating parameter associated with one of the plurality of set points.

13 . The apparatus of claim 12 , wherein the memory controller is configured to write a fourth value to a register of the plurality of registers, wherein the fourth value comprises an operating parameter associated with a different one of the plurality of set points.

14 . The apparatus of claim 12 , wherein the operating parameter comprises at least one of a burst length operating parameter, a preamble operating parameter, a precharge operating parameter, a postamble operating parameter, a latency parameter, or a drive strength parameter, a data bus interface operating parameter, an on-die termination operating parameter, or a voltage reference operating parameter.

15 . An apparatus comprising:
a memory controller configured to:
provide a training pattern to a memory device;
evaluate a performance of the memory device based on the training pattern; and
write a value of a respective parameter value of an operating parameter associated with a first one of a plurality of set points.

16 . The apparatus of claim 15 , wherein the training pattern includes at least one of a command signal, an address signal, or data signal.

17 . The apparatus of claim 15 , wherein the training pattern includes a signal and a parameter of the signal is varied in the training pattern.

18 . The apparatus of claim 17 , wherein the parameter of the signal includes at least one of a signal timing, a voltage range, or an on-die termination setting.

19 . The apparatus of claim 11 , wherein a second parameter of the signal is held constant in the training pattern.

20 . The apparatus of claim 15 , wherein the memory controller is further configured to:
provide a second training pattern to the memory device; evaluate the performance of the memory device based on the second training pattern; and write a value of the respective parameter value of the operating parameter associated with a second one of the plurality of set points.

Assignees

• Lodestar Licensing Group Llc

Inventors

• Gans Dean D
• Skinner Daniel C

Classifications

• G11C7/109

  Control signal input circuits · CPC title

• G11C7/1051

  Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits · CPC title

• G11C7/1045 Primary

  Read-write mode select circuits · CPC title