A computer processor

Patent metadata

Field	Value
Publication number	US-2025238395-A1
Application number	US-202318853927-A
Country	US
Kind code	A1
Filing date	Mar 29, 2023
Priority date	Apr 12, 2022
Publication date	Jul 24, 2025
Grant date	—

Abstract

A processing element array of a processor, comprising a plurality of processing elements or nodes, each of the processing elements including at least one instruction register, a control unit, at least one arithmetic or logic unit, and one or more storage elements, and being configured to store, decode and execute an instruction; the instruction register and the storage elements are configured to be writable from one or more data buses; and the arithmetic or logic unit is configured to receive input from one of the storage elements and to output a result to one or more other processing elements of the array of processing elements via the one or more data buses. Also, a fabric cell or tile of a processor, comprising such a processing element array, an S bus that constitutes the data bus, and a cell or tile interface node. The interface node connects an external message bus to the S bus of the fabric cell; the S bus implements the datapath of the processing elements, and facilitates data exchange between the processing elements, and between the interface node and the cell or tile interface node and processing elements; and the interface node comprises a plurality of message registers and is configured to forward instructions to the processing elements, coordinate eviction and restoring locally, and assist the processing elements during the execution of communication and fragment instance management instructions.

First claim

1 . A processing element array of a processor, comprising:
a plurality of processing elements or nodes, each of the processing elements including at least one instruction register, a control unit, at least one arithmetic or logic unit, and one or more storage elements, and being configured to store, decode and execute an instruction; wherein the instruction register and the storage elements are configured to be writable from one or more data buses; and the arithmetic or logic unit is configured to receive input from one of the storage elements and to output a result to one or more other processing elements of the array of processing elements via the one or more data buses.

2 . An array as claimed in claim 1 , wherein the arithmetic or logic unit is configured to pass the result to one or more storage elements of the other processing elements of the array of processing elements.

3 . An array as claimed in either claim 1 , wherein each of the processing elements includes a third storage element writable from the data bus and a multiplexer intermediate the first storage element and the arithmetic-logic unit, the multiplexer being configured to receive inputs from the first and third storage elements and to pass selected outputs to the arithmetic-logic unit.

4 . An array as claimed in claim 1 , wherein each of the processing elements includes a control unit configured such that when an instruction encodes a conditional branch, the control unit determines a branch decision based on a send type of the instruction and the result outputted by the arithmetic-logic unit being zero.

5 . An array as claimed in claim 1 , wherein the instructions encode operations that are basic enough to require no intermediate translation into microinstructions before execution.

6 . An array as claimed in claim 1 , wherein the instructions have respective formats that facilitate simple fetching and decoding.

7 . An array as claimed in claim 1 , wherein the instructions support a minimal set of operand types and less common operand types require dedicated instructions.

8 . An array as claimed in claim 7 , wherein each of the processing elements receives input data primarily from two storage elements that are statically associated with the respective processing element.

9 . An array as claimed in claim 1 , wherein
the instruction register of a first processing element of the plurality of processing elements supports a plurality of target instruction pointers, defining respective logical connections between the first processing element and one or more other processing elements of the plurality of processing elements; one or more of the target instruction pointers are configured for dataflow coordination or control flow coordination; and one or more of the target instruction pointers are configured for dataflow coordination.

10 . A fabric cell or tile of a processor, comprising:
a processing element array as claimed in claim 1 ; an S bus that constitutes the data bus; and a cell or tile interface node; wherein the interface node connects an external message bus to the S bus of the fabric cell; the S bus implements the datapath of the processing elements, and facilitates data exchange between the processing elements, and between the interface node and the cell or tile interface node and processing elements; the interface node comprises a plurality of message registers and is configured to forward instructions to the processing elements, coordinate eviction and restoring locally, and assist the processing elements during the execution of communication and fragment instance management instructions.

11 . A fabric cell or tile as claimed in claim 10 , comprising one or more S/T links for connecting the S bus to respective S buses of one or more adjacent fabric cells or tiles via respective T links.

12 . A fabric cell or tile as claimed in claim 11 , wherein the interface node serves as an interface for a plurality of like fabric cells or tiles.

13 . A processor, comprising:
a plurality of fabric cells or tiles as claimed in claim 10 ; a message bus; a fragment instance manager; a fragment instance table; and a memory.

14 . A processor as claimed in claim 13 , implementing dynamic tiling so as to support linkage of a plurality of tiles.

Assignees

• Univ Berlin Tech

Inventors

• Kaiser Tobias

Classifications

• G06F15/7867

  with reconfigurable architecture · CPC title

• G06F15/76

  Architectures of general purpose stored program computers (with program plugboard G06F15/08; multicomputers G06F15/16) · CPC title

• G06F15/8046 Primary

  Systolic arrays · CPC title