Data compression

Patent metadata

Field	Value
Publication number	US-2025238132-A1
Application number	US-202418893614-A
Country	US
Kind code	A1
Filing date	Sep 23, 2024
Priority date	Jan 23, 2024
Publication date	Jul 24, 2025
Grant date	—

Abstract

Disclosed is a storage device, which includes a nonvolatile memory device that stores or reads user data and a controller that controls the nonvolatile memory device, and the nonvolatile memory device includes a memory cell array including a plurality of memory cells that stores data bits corresponding to the user data, a compression circuit that compresses soft-bit data sensed from the plurality of memory cells, and control logic that controls the compression circuit through a plurality of compression stages and transmits a stage control signal to the compression circuit to control whether compression on each of the plurality of compression stages is performed.

First claim

What is claimed is:

1 . A storage device comprising:
a nonvolatile memory device configured to store and read user data; and a controller configured to control the nonvolatile memory device, wherein the nonvolatile memory device includes:
a memory cell array including a plurality of memory cells configured to store data bits corresponding to the user data,
a compression circuit configured to compress, in a plurality of compression stages, soft-bit data sensed from the plurality of memory cells, and
control logic configured to transmit a stage control signal to the compression circuit,
wherein the stage control signal controls whether compression in each of the plurality of compression stages is performed.

2 . The storage device of claim 1 , wherein input data and output data of each of the plurality of compression stages include at least one same index code, and
wherein the at least one same index code corresponds to a position of a weak bit in the soft-bit data.

3 . The storage device of claim 1 , wherein, in at least one compression stage of the plurality of compression stages, output data generated by compressing input data in a previous compression stage is compressed at a preset compression ratio.

4 . The storage device of claim 1 , wherein the control logic is configured to transmit different stage control signals to the compression circuit based on a compression ratio for the soft-bit data.

5 . The storage device of claim 1 , wherein each of the plurality of compression stages is performed by a corresponding stage compression circuit of a plurality of stage compression circuits included in the compression circuit, and
wherein each of the plurality of stage compression circuits is configured to:
receive input data including a plurality of pieces of cell data, and
select, as output data, at least a portion of the plurality of pieces of cell data,
wherein each of the plurality of pieces of cell data is composed of one of a dummy code or an index code, and
wherein the index code corresponds to a position of a weak bit in the soft-bit data.

6 . The storage device of claim 5 , wherein a configuration of inputs and outputs between the plurality of stage compression circuits is controlled by the stage control signal.

7 . The storage device of claim 5 , wherein the compression circuit includes a converting circuit configured to convert the weak bit of the soft-bit data into the index code based on a preset mapping table, and
wherein the preset mapping table represents a mapping between the index code and a position or order of soft-bits included in the soft-bit data.

8 . The storage device of claim 5 , wherein the plurality of compression stages include a first compression stage and a second compression stage,
wherein the plurality of stage compression circuits include a first stage compression circuit configured to perform the first compression stage and a second stage compression circuit configured to perform the second compression stage, and wherein each of the first stage compression circuit and the second stage compression circuit is configured to generate corresponding output data by selecting a portion of cell data from corresponding input data, based on a corresponding stage compression ratio.

9 . The storage device of claim 8 , wherein the corresponding stage compression ratios of the first stage compression circuit and the second stage compression circuit are different.

10 . The storage device of claim 5 , wherein each of the plurality of stage compression circuits is configured to preferentially select the index code when selecting at least the portion of the plurality of pieces of cell data.

11 . The storage device of claim 1 , wherein the control logic is configured to control a number of utilized stages in the plurality of compression stages based on a target compression ratio.

12 . The storage device of claim 1 , wherein the compression circuit is configured to compress the soft-bit data with a first compression ratio during a first time period and compress the soft-bit data with a second compression ratio during a second time period,
wherein the second time period is a period after the first time period, and wherein the second compression ratio is less than the first compression ratio.

13 . The storage device of claim 12 , wherein the control logic is configured to provide a compression ratio change signal to the controller in response to a change from the first compression ratio to the second compression ratio,
wherein the compression circuit is configured to generate output data by compressing input data including an index code and a dummy code, wherein the compression circuit is configured to generate the compression ratio change signal to include a code not included in a mapping table, and wherein the index code comprises a code converted based on the mapping table in which a weak bit of the soft-bit data is preset.

14 . The storage device of claim 12 , wherein the compression circuit is configured to generate output data by compressing input data including an index code and a dummy code,
wherein the compression circuit is configured to perform compression based on a first mapping table when using the first compression ratio, and to perform compression based on a second mapping table when using the second compression ratio, wherein the controller is configured to determine a change from the first compression ratio to the second compression ratio based on a bit configuration of a first bit sequence, in the output data, having a size corresponding to the first compression ratio, and wherein the index code comprises a code converted based on a mapping table in which a weak bit of the soft-bit data is preset.

15 . The storage device of claim 14 , wherein the compression circuit is configured to use a last index code of the second mapping table as the dummy code when using the first compression ratio, and to perform compression using a last index code of the first mapping table when using the second compression ratio.

16 . The storage device of claim 1 , wherein a compression ratio applied by the compression circuit is independent of a bit configuration of input data.

17 . The storage device of claim 16 , wherein a compression ratio applied by the compression circuit is changed based on a remaining lifespan of the memory cell array.

18 . A method comprising:
transmitting, by a controller configured to control a nonvolatile memory device, a soft read command to the nonvolatile memory device; generating, by the nonvolatile memory device, soft-bit data in response to the soft read command; providing, by a control logic circuit of the nonvolatile memory device, a stage control signal to a compression circuit, to control compression by the compression circuit in a plurality of compression stages; generating, by the compression circuit, compressed soft-bit data by compressing the soft-bit data based on the stage control signal; and transmitting, by the nonvolatile memory device, the compressed soft-bit data to the controller, wherein the stage control signal controls whether compression in each of the plurality of compression stages is performed.

19 . The method of claim 18 , further comprising:
changing, by the control logic circuit, a compression ratio applied by the compression circuit; and transmitting, by the control logic circuit, a signal corresponding to the change in the compression ratio to the controller.

20 . A s

Assignees

• Samsung Electronics Co Ltd

Inventors

• Moon Young Sik
• Jang Jae Hun
• Yoo Hyunjoon
• Kang Soonyoung
• Na Hanbyeul
• Shin Junho

Classifications

• G11C29/42

  using error correcting codes [ECC] or parity check · CPC title

• G11C16/34

  Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention · CPC title

• G11C16/24

  Bit-line control circuits · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C16/12

  Programming voltage switching circuits · CPC title