Overhang pattern for advanced oled patterning

Patent metadata

Field	Value
Publication number	US-2025234720-A1
Application number	US-202419006989-A
Country	US
Kind code	A1
Filing date	Dec 31, 2024
Priority date	Jan 16, 2024
Publication date	Jul 17, 2025
Grant date	—

Abstract

Embodiments described herein relate to a sub-pixel circuit and methods of forming a sub-pixel circuit. The sub-pixel circuit include adjacent overhang structures, an anode, an organic light emitting diode (OLED) material disposed over the anode, and a cathode disposed over the OLED material. The OLED material extends under the adjacent overhang structures. The cathode extends under the adjacent overhang structures. The overhang structures are defined by an overhang extension of a second structure extending laterally past a first structure. The first structure is disposed over a substrate. The first structure includes a lower section having a first lateral etching rate and an upper section deposited over the lower section having a second lateral etching rate. The second lateral etching rate is different from the first lateral etching rate.

First claim

What is claimed is:

1 . A sub-pixel circuit, comprising:
adjacent overhang structures, the overhang structures defined by an overhang extension of a second structure extending laterally past a first structure, the first structure disposed over a substrate, wherein the first structure comprises:
a lower section having a first lateral etching rate;
an upper section deposited over the lower section having a second lateral etching rate, wherein the second lateral etching rate is different from the first lateral etching rate;
an anode; an organic light emitting diode (OLED) material disposed over the anode, wherein the OLED material extends under the adjacent overhang structures; and a cathode disposed over the OLED material, the cathode extending under the adjacent overhang structures.

2 . The sub-pixel of claim 1 , wherein:
the lower section is deposited at a first temperature is about 250° C. to about 350° C.; and the upper section is deposited at a second temperature of about 100° C. to about 200° C.

3 . The sub-pixel of claim 1 , wherein:
an upper surface of the second structure has a first width; and a bottom surface of the first structure has a second width, wherein the first width of the upper surface is equal to the second width of the bottom surface.

4 . The sub-pixel of claim 1 , wherein the material of the upper section and the lower section include amorphous silicon (a-Si), silicon nitride (Si 3 N 4 ), silicon oxide (SiO 2 ), silicon oxynitride (Si 2 N 2 O), or combinations thereof.

5 . The sub-pixel of claim 1 , wherein the material of the upper section is the same as the material of the lower section.

6 . The sub-pixel of claim 1 , wherein the second structure includes copper (Cu), aluminum (Al), aluminum neodymium (AlNd), molybdenum (Mo), molybdenum tungsten (MoW), or combinations thereof.

7 . The sub-pixel of claim 1 , wherein the second structure includes amorphous silicon (a-Si), silicon nitride (Si 3 N 4 ), silicon oxide (SiO 2 ), silicon oxynitride (Si 2 N 2 O), germanium (Ge), germanium arsenide (GeAs III or IV), or combinations thereof.

8 . A device, comprising:
a substrate; a plurality of adjacent pixel-isolation structures (PIS) disposed over the substrate; a plurality of sub-pixels, each sub-pixel comprising:
adjacent overhang structures, the overhang structures defined by an overhang extension of a second structure extending laterally past a first structure, the first structure disposed over a substrate; wherein the first structure comprises:
a first endpoint of a bottom surface of the first structure may extend to or past a first edge of the PIS; and
a second endpoint of the bottom surface of the first structure may extend to or past a second edge the PIS;
a lower section having a first lateral etching rate;
an upper section deposited over the lower section having a second lateral etching rate, wherein the second lateral etching rate is different from the first lateral etching rate;

an anode;
an organic light emitting diode (OLED) material disposed over the anode, wherein the OLED material extends under the adjacent overhang structures; and
a cathode disposed over the OLED material, the cathode extending under the adjacent overhang structures.

9 . The device of claim 8 , wherein:
the lower section is deposited at a first temperature is about 250° C. to about 350° C.; and the upper section is deposited at a second temperature of about 100° C. to about 200° C.

10 . The device of claim 8 , wherein the second structure includes copper (Cu), aluminum (Al), aluminum neodymium (AlNd), molybdenum (Mo), molybdenum tungsten (MoW), or combinations thereof.

11 . The device of claim 8 , wherein the second structure includes amorphous silicon (a-Si), silicon nitride (Si 3 N 4 ), silicon oxide (SiO 2 ), silicon oxynitride (Si 2 N 2 O), germanium (Ge), germanium arsenide (GeAs III or IV), or combinations thereof.

12 . The device of claim 8 , wherein:
an upper surface of the second structure has a first width; and the bottom surface of the first structure has a second width, wherein the first width of the upper surface is equal to the second width of the bottom surface.

13 . The device of claim 12 , wherein the first width and the second width are about 0.5 μm to about 2 μm.

14 . The device of claim 8 , wherein the material of the upper section and the lower section include amorphous silicon (a-Si), silicon nitride (Si 3 N 4 ), silicon oxide (SiO 2 ), silicon oxynitride (Si 2 N 2 O), or combinations thereof.

15 . The device of claim 8 , wherein the material of the upper section is the same as the material of the lower section.

16 . A method of forming a sub-pixel circuit, comprising:
disposing a lower section layer having a first lateral etching rate over a substrate, wherein an anode is deposited on the substrate; disposing an upper section layer having a second lateral etching rate over the lower section layer, wherein the first lateral etching rate is different from the second lateral etching rate, and wherein the lower section layer and the upper section layer form a first structure layer; depositing a second structure layer over the first structure layer; and removing portions of the first structure layer and the second structure layer exposed by a resist to form adjacent overhang structures defined by an overhang extension of a second structure formed from the second structure layer extending laterally past a first structure formed from the first structure layer, the first structure disposed over the substrate, wherein the first structure comprises:
an upper section formed from the upper section layer; and
a lower section formed from the lower section layer.

17 . The method of claim 16 , wherein:
the lower section is deposited at a first temperature is about 250° C. to about 350° C.; and the upper section is deposited at a second temperature of about 100° C. to about 200° C.

18 . The method of claim 16 , wherein:
an upper surface of the second structure has a first width; and a bottom surface of the first structure has a second width, wherein the first width of the upper surface is equal to the second width of the bottom surface.

19 . The method of claim 16 , further comprising:
depositing an organic light emitting diode (OLED) material layer, a cathode layer, and an encapsulation layer material; and removing portions of the OLED material the cathode layer, and the encapsulation layer material to form an OLED material, a cathode, and an encapsulation layer.

20 . The method of claim 16 , wherein a material of the upper section and the lower section include amorphous silicon (a-Si), silicon nitride (Si 3 N 4 ), silicon oxide (SiO 2 ), silicon oxynitride (Si 2 N 2 O), or combinations thereof, and wherein the material of the upper section is the same as the material of the lower section.

Assignees

• Applied Materials Inc

Inventors

• Lee Jungmin
• Haas Dieter
• Mcdaniel Grgory Max
• Lin Yu-Hsin

Classifications

• H10K59/80521

  characterised by their shape · CPC title

• H10K2102/361

  Temperature · CPC title

• H10K59/122 Primary

  Pixel-defining structures or layers, e.g. banks · CPC title

• H10K59/1201 Primary

  Manufacture or treatment · CPC title