Pixel circuit and driving method therefor, and display panel

Patent metadata

Field	Value
Publication number	US-2025232727-A1
Application number	US-202519059272-A
Country	US
Kind code	A1
Filing date	Feb 21, 2025
Priority date	Aug 30, 2022
Publication date	Jul 17, 2025
Grant date	—

Abstract

A pixel circuit and a driving method therefor, and a display panel are disclosed. The pixel circuit includes a drive module, a data writing module, and a light-emitting module. The data writing module includes a first transistor (T 1 ) and a second transistor (T 2 ) that are connected in series. The first transistor (T 1 ) is a low-temperature polysilicon transistor, and the second transistor (T 2 ) is an oxide transistor. The data writing module is configured to transmit a data voltage (Vdata) to the drive module. The drive module is configured to drive, based on the data voltage (Vdata), the light-emitting module to emit light.

First claim

What is claimed is:

1 . A pixel circuit, comprising: a drive module, a data writing module, and a light-emitting module, wherein
the data writing module comprises a first transistor and a second transistor that are connected in series, the first transistor is a low-temperature polysilicon transistor, the second transistor is an oxide transistor, and the data writing module is configured to transmit a data voltage to the drive module; and the drive module is configured to drive, based on the data voltage, the light-emitting module to emit light.

2 . The pixel circuit according to claim 1 , wherein in a display period of the pixel circuit, the second transistor is turned on prior to the first transistor, and the first transistor is turned on in a period in which the second transistor is turned on.

3 . The pixel circuit according to claim 1 , wherein the first transistor and the second transistor are sequentially connected in series between a data line and the drive module.

4 . The pixel circuit according to claim 1 , further comprising a storage module, a light-emitting control module, and an initialization module, wherein the storage module is connected to the drive module, and the storage module is configured to store the data voltage; the storage module comprises a first storage module and a second storage module; the drive module comprises a dual-gate transistor, the light-emitting control module, the dual-gate transistor, and the light-emitting module are sequentially connected between a first power supply and a second power supply, a first electrode of the dual-gate transistor is connected to the light-emitting control module, and a second electrode of the dual-gate transistor is connected to the light-emitting module;
the data writing module is connected between a first gate of the dual-gate transistor and a data line, and the data writing module is configured to transmit a data voltage output by the data line to the first gate; the first storage module is connected between the first gate and the second electrode of the dual-gate transistor, the first storage module is configured to store a voltage at the first gate, the second storage module is connected between a second gate and the second electrode of the dual-gate transistor, and the second storage module is configured to store a voltage at the second gate; and the initialization module is configured to initialize the first gate, the second gate, the first electrode, and the second electrode of the dual-gate transistor.

5 . The pixel circuit according to claim 4 , wherein the initialization module comprises a first initialization module, a second initialization module, and a third initialization module, the first initialization module is connected between the first gate and the second electrode of the dual-gate transistor, and the second initialization module is connected between the second gate and the first electrode of the dual-gate transistor; and
the third initialization module is connected between the second electrode of the dual-gate transistor and an initialization signal line.

6 . The pixel circuit according to claim 5 , wherein a signal on the initialization signal line is provided by the second power supply.

7 . The pixel circuit according to claim 5 , wherein the first gate is a top gate, and the second gate is a bottom gate; the first initialization module comprises a third transistor, the second initialization module comprises a fourth transistor, the third initialization module comprises a fifth transistor, and the light-emitting control module comprises a sixth transistor; the first storage module comprises a first capacitor, and the second storage module comprises a second capacitor;
a first electrode of the first transistor is connected to the data line, a second electrode of the first transistor is connected to a first electrode of the second transistor, a gate of the first transistor is connected to a first scan line, a second electrode of the second transistor is connected to the first gate of the dual-gate transistor, and a gate of the second transistor is connected to a second scan line; a first electrode of the third transistor is connected to the second electrode of the dual-gate transistor, a second electrode of the third transistor is connected to the first gate of the dual-gate transistor, a gate of the third transistor is connected to a third scan line, a first electrode of the fourth transistor is connected to the first electrode of the dual-gate transistor, a second electrode of the fourth transistor is connected to the second gate of the dual-gate transistor, and a gate of the fourth transistor is connected to the third scan line; a first electrode of the fifth transistor is connected to the initialization signal line, a second electrode of the fifth transistor is connected to the second electrode of the dual-gate transistor, and a gate of the fifth transistor is connected to the second scan line; a first electrode of the sixth transistor is connected to the first power supply, a second electrode of the sixth transistor is connected to the first electrode of the dual-gate transistor, and a gate of the sixth transistor is connected to a light-emitting control signal line; and the first capacitor is connected between the first gate and the second electrode of the dual-gate transistor, and the second capacitor is connected between the second gate and the second electrode of the dual-gate transistor.

8 . The pixel circuit according to claim 7 , wherein the sixth transistor is a low-temperature polysilicon transistor, and the dual-gate transistor, the third transistor, the fourth transistor, and the fifth transistor are all oxide transistors.

9 . The pixel circuit according to claim 1 , further comprising a storage module, a light-emitting control module, a compensation module, and an initialization module, wherein the storage module is connected to the drive module, and the storage module is configured to store the data voltage; the storage module comprises a first storage module and a second storage module; the light-emitting control module, the drive module, and the light-emitting module are sequentially connected between a first power supply and a second power supply;
the first storage module is connected between the data writing module and a control terminal of the drive module, and the first storage module is configured to couple the data voltage to the drive module;
the compensation module is connected in parallel to the first storage module, and a first terminal of the drive module is connected to the light-emitting control module, or the compensation module is connected between the control terminal and a first terminal of the drive module, and the first terminal of the drive module is connected to the light-emitting control module;
the second storage module is connected between the data writing module and a second terminal of the drive module or the second storage module is connected between the first storage module and a second terminal of the drive module, and the second storage module is configured to couple a voltage at the second terminal of the drive module to the first storage module; and the initialization module is configured to initialize the first storage module and the second storage module.

10 . The pixel circuit according to claim 9 , wherein the initialization module comprises a first initialization module and a second initialization module, the first initialization module is connected between the first initialization signal line and a first terminal of the first storage module, and a second terminal of the first storage module is connected to the control terminal of the drive modul

Assignees

• Yungu Gu’An Tech Co Ltd

Inventors

• Gai Cuili
• Guo Enqing
• Li Junfeng
• Xing Rubo
• Pan Kangguan

Classifications

• G09G2300/0852

  being a dynamic memory with more than one capacitor · CPC title

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title