Pixel of a display device, and display device

Patent metadata

Field	Value
Publication number	US-2025232711-A1
Application number	US-202418977136-A
Country	US
Kind code	A1
Filing date	Dec 11, 2024
Priority date	Jan 16, 2024
Publication date	Jul 17, 2025
Grant date	—

Abstract

A pixel includes a first transistor including a first and second gates, a first capacitor connected between a first node and a third node, a second capacitor connected between a fourth node and the third node, a second transistor receiving a first scan signal and connected between a data line and the first node, a third transistor receiving a second scan signal and connected between a reference voltage line and the first node, a fourth transistor receiving a third scan signal and connected between an initialization line and the third node, a fifth transistor receiving an emission signal and connected between a first power line and the second node, a sixth transistor receiving the second scan signal and connected between the fourth node and the second node, and a light emitting element connected between the third node and a second power line.

First claim

What is claimed is:

1 . A pixel of a display device, the pixel comprising:
a first transistor including a first gate connected to a first node, a first terminal connected to a second node, a second terminal connected to a third node, and a second gate connected to a fourth node; a first capacitor including a first electrode connected to the first node, and a second electrode connected to the third node; a second capacitor including a first electrode connected to the fourth node, and a second electrode connected to the third node; a second transistor including a gate which receives a first scan signal, a first terminal connected to a data line which transfers a data voltage, and a second terminal connected to the first node; a third transistor including a gate which receives a second scan signal, a first terminal connected to a line which transfers a reference voltage, and a second terminal connected to the first node; a fourth transistor including a gate which receives a third scan signal, a first terminal connected to a line which transfers an initialization voltage, and a second terminal connected to the third node; a fifth transistor including a gate which receives an emission signal, a first terminal connected to a line which transfers a first power supply voltage, and a second terminal connected to the second node; a sixth transistor including a gate which receives the second scan signal, a first terminal connected to the fourth node, and a second terminal connected to the second node; and a light emitting element connected between the third node, and a line which transfers a second power supply voltage.

2 . The pixel of claim 1 , wherein the first capacitor stores a voltage difference between the data voltage and the initialization voltage, and
wherein the second capacitor stores a threshold voltage of the first transistor.

3 . The pixel of claim 1 , wherein, in a compensation period,
the third transistor applies the reference voltage to the first node, the fourth transistor applies the initialization voltage to the third node, the sixth transistor diode-connects the first transistor by connecting the fourth node to the second node, and the second capacitor stores a threshold voltage of the first transistor in a diode connection manner.

4 . The pixel of claim 3 , wherein the initialization voltage is higher than the reference voltage.

5 . The pixel of claim 4 , wherein, in the compensation period, a negative gate-source voltage is applied to the first transistor, and the threshold voltage of the first transistor is shifted in a positive direction.

6 . The pixel of claim 1 , wherein the first gate of the first transistor is a top gate located above an active region, and
wherein the second gate of the first transistor is a bottom gate located under the active region.

7 . The pixel of claim 1 , wherein the first gate of the first transistor is a bottom gate located under an active region, and
wherein the second gate of the first transistor is a top gate located above the active region.

8 . The pixel of claim 1 , wherein the third scan signal is same as the second scan signal.

9 . The pixel of claim 1 , further comprising:
a seventh transistor including a gate which receives a fourth scan signal, a first terminal connected to the line which transfers the first power supply voltage, and a second terminal connected to the fourth node.

10 . The pixel of claim 9 , wherein frame periods for the display device include a compensation frame period in which the pixel performs a threshold voltage compensation operation, and a non-compensation frame period in which the pixel does not perform the threshold voltage compensation operation.

11 . The pixel of claim 10 , wherein the compensation frame period comprises:
an initialization period in which the third node and the fourth node are initialized; a compensation period in which the threshold voltage compensation operation is performed to store a threshold voltage of the first transistor in the second capacitor; a writing period in which a voltage difference between the data voltage and the initialization voltage is stored in the first capacitor; and an emission period in which the light emitting element emits light.

12 . The pixel of claim 11 , wherein, in the initialization period,
the third scan signal and the fourth scan signal have an on-level, the first scan signal, the second scan signal and the emission signal have an off-level, the fourth transistor is turned on in response to the third scan signal having the on-level, and applies the initialization voltage to the third node, the seventh transistor is turned on in response to the fourth scan signal having the on-level, and applies the first power supply voltage to the fourth node, the third node is initialized based on the initialization voltage, and the fourth node is initialized based on the first power supply voltage.

13 . The pixel of claim 11 , wherein, in the compensation period,
the second scan signal and the third scan signal have an on-level, the first scan signal, the fourth scan signal and the emission signal have an off-level, the third transistor is turned on in response to the second scan signal having the on-level, and applies the reference voltage to the first node, the fourth transistor is turned on in response to the third scan signal having the on-level, and applies the initialization voltage to the third node, the sixth transistor is turned on in response to the second scan signal having the on-level, and diode-connects the first transistor by connecting the fourth node to the second node, and the second capacitor stores the threshold voltage of the first transistor in a diode connection manner.

14 . The pixel of claim 11 , wherein, in the writing period,
the first scan signal and the third scan signal have an on-level, the second scan signal, the fourth scan signal and the emission signal have an off-level, the second transistor is turned on in response to the first scan signal having the on-level, and applies the data voltage to the first node, the fourth transistor is turned on in response to the third scan signal having the on-level, and applies the initialization voltage to the third node, and the first capacitor stores the voltage difference between the data voltage and the initialization voltage.

15 . The pixel of claim 11 , wherein, in the emission period,
the emission signal has an on-level, the first scan signal, the second scan signal, the third scan signal and the fourth scan signal have an off-level, the fifth transistor is turned on in response to the emission signal having the on-level, and connects the line which transfers the first power supply voltage and the second node, the first transistor generates a driving current based on the voltage difference between the data voltage and the initialization voltage stored in the first capacitor, and the threshold voltage of the first transistor stored in the second capacitor, and the light emitting element emits light based on the driving current.

16 . The pixel of claim 10 , wherein the non-compensation frame period comprises:
a writing period in which a voltage difference between the data voltage and the initialization voltage is stored in the first capacitor; and an emission period in which the light emission element emits light, and wherein the non-compensation frame period does not include an initialization period and a compensation period.

17 . The pixel of claim 9 , wherein the first t

Assignees

• Samsung Display Co Ltd

Inventors

• Shim Jongsik
• Kwon Soon-Gi
• Kim Donghyun
• Min Junyoung
• An jun-yong
• Yang Chanyoung
• Lee Seunghee
• Choi Junwon

Classifications

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G2320/0209

  Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display · CPC title

• G09G3/3674

  Details of drivers for scan electrodes · CPC title

• G09G3/3266

  Details of drivers for scan electrodes · CPC title

• G09G3/3208

  organic, e.g. using organic light-emitting diodes [OLED] · CPC title