Nand data placement schema

Patent metadata

Field	Value
Publication number	US-2025226041-A1
Application number	US-202519093992-A
Country	US
Kind code	A1
Filing date	Mar 28, 2025
Priority date	Mar 16, 2018
Publication date	Jul 10, 2025
Grant date	—

Abstract

Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios. The present disclosure stripes data diagonally across page lines and planes to enhance the data protection. Parity bits are stored in SLC blocks for extra protection until the block is finished writing and then the parity bits may be deleted.

First claim

1 . A memory controller device comprising:
a hardware processor configured to perform operations comprising:
receiving a data item from a host over a host interface;
diagonally striping the data item across pages and dies of NAND memory cells by:
programming a first portion of the received data item into an array of NAND memory cells at a first page of a first die;
programming a second portion of the received data item into the array of NAND memory cells at a second page of a second die;
programming a third portion of the received data item into the array of NAND memory cells at a third page of a third die; and
wherein each data portion of the received data item is programmed on a different page line than every other data portion.

2 . The memory controller device of claim 1 , wherein a first page line number of the first page is greater than a second page line number of the second page, and the second page line number is greater than a third page line number of the third page.

3 . The memory controller device of claim 1 , wherein a second page line number of the second page is between a first page line number of the first page and a third page line number of the third page.

4 . The memory controller device of claim 1 , wherein the first, second, and third portions comprise a lower page, an upper page, and an extra page.

5 . The memory controller device of claim 1 , wherein the operations further comprise calculating a parity value for the received data item based on the first portion, the second portion, and the third portion.

6 . The memory controller device of claim 5 , wherein the parity value is stored in a parity page.

7 . The memory controller device of claim 5 , wherein the operations further comprise:
determining that one of the first, second, or third portions are corrupted; responsive to determining that the one of the first, second, or third portions are corrupted, reconstructing the corrupted one of the first, second, or third portions using the parity value.

8 . A method for storing data in a memory device, the method comprising:
receiving a data item from a host over a host interface; diagonally striping the data item across pages and dies of NAND memory cells by:
programming a first portion of the received data item into an array of NAND memory cells at a first page of a first die;
programming a second portion of the received data item into the array of NAND memory cells at a second page of a second die;
programming a third portion of the received data item into the array of NAND memory cells at a third page of a third die; and
wherein each data portion of the received data item is programmed on a different page line than every other data portion.

9 . The method of claim 8 , wherein a first page line number of the first page is greater than a second page line number of the second page, and the second page line number is greater than a third page line number of the third page.

10 . The method of claim 8 , wherein a second page line number of the second page is between a first page line number of the first page and a third page line number of the third page.

11 . The method of claim 8 , wherein the first, second, and third portions comprise a lower page, an upper page, and an extra page.

12 . The method of claim 8 , wherein the method further comprises calculating a parity value for the received data item based on the first portion, the second portion, and the third portion.

13 . The method of claim 12 , wherein the parity value is stored in a parity page.

14 . The method of claim 12 , further comprising:
determining that one of the first, second, or third portions are corrupted; responsive to determining that the one of the first, second, or third portions are corrupted, reconstructing the corrupted one of the first, second, or third portions using the parity value.

15 . A non-transitory, machine-readable medium, storing instructions for storing data in a memory device, the instructions when executed, cause the memory device to perform operations comprising:
receiving a data item from a host over a host interface; diagonally striping the data item across pages and dies of NAND memory cells by:
programming a first portion of the received data item into an array of NAND memory cells at a first page of a first die;
programming a second portion of the received data item into the array of NAND memory cells at a second page of a second die;
programming a third portion of the received data item into the array of NAND memory cells at a third page of a third die; and
wherein each data portion of the received data item is programmed on a different page line than every other data portion.

16 . The non-transitory machine-readable medium of claim 15 , wherein a first page line number of the first page is greater than a second page line number of the second page, and the second page line number is greater than a third page line number of the third page.

17 . The non-transitory machine-readable medium of claim 15 , wherein a second page line number of the second page is between a first page line number of the first page and a third page line number of the third page.

18 . The non-transitory machine-readable medium of claim 15 , wherein the first, second, and third portions comprise a lower page, an upper page, and an extra page.

19 . The non-transitory machine-readable medium of claim 15 , wherein the method further comprises calculating a parity value for the received data item based on the first portion, the second portion, and the third portion.

20 . The non-transitory machine-readable medium of claim 19 , wherein the parity value is stored in a parity page.

Assignees

• Micron Technology Inc

Inventors

• Manganelli Carminantonio
• Papa Paolo
• Laculo Massimo
• D'Eliseo Giuseppe
• Sassara Alberto

Classifications

• H03K19/02

  using specified components ({H03K19/0005 - H03K19/0021}, H03K19/003 - H03K19/0175 take precedence) · CPC title

• H03K19/21

  EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical · CPC title

• G11C29/42

  using error correcting codes [ECC] or parity check · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/102

  External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators · CPC title