Computational storage device, method for operating the computational storage device and method for operating host device

US2025224902A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2025224902-A1
Application numberUS-202519094669-A
CountryUS
Kind codeA1
Filing dateMar 28, 2025
Priority dateOct 24, 2022
Publication dateJul 10, 2025
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method for operating a computational storage device includes receiving by a storage controller and from a host device: (1) a compute namespace setting instruction instructing the setting of a compute namespace; (2) a latency threshold value related to the compute namespace; (3) a program; (4) a first execute command using the program; and (5) a second execute command using the program. Additionally, the method includes transmitting, by the storage controller and to the host device, a latency message in response to the second execute command.

First claim

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1 . A computational storage device comprising: a non-volatile memory to store data therein; a storage controller configured to control the non-volatile memory; and a first accelerator configured to process computing on the data based on an execute command received from a first host device and using a first program provided from the first host device, wherein: the execute command includes a first execute command and a second execute command, the storage controller is configured to: receive a first compute namespace setting instruction establishing a first compute namespace, a first latency threshold value related to the first compute namespace, a first program, a first execute command using the first program and a second execute command using the first program; in response to a latency-related state being: a first state while storing the second execute command received from the first host device in a first command queue to await processing by the first accelerator, store the second execute command in the first command queue, and a second state different from the first state, transmit a first latency message to the first host device. 2 . The computational storage device of claim 1 , wherein at least some components of the storage controller and the first accelerator are set, by the first host device, as a first compute namespace used to process the computing based on the execute command received from the first host device. 3 . The computational storage device of claim 1 , wherein the first state is a state in which a sum is equal to or smaller than the first latency threshold value, the sum acquired by adding: a first processing time required to process a first computing based on the first execute command using the first accelerator; and a second processing time required to process a second computing based on the second execute command using the first accelerator, and the second state is a state in which the sum is greater than the first latency threshold value. 4 . The computational storage device of claim 1 , further comprising: receiving, by the storage controller and from a second host device, a second compute namespace setting instruction establishing a second compute namespace different from the first compute namespace setting instruction, a second latency threshold value related to the second compute namespace, a second program different from the first program, a third execute command using the second program and a fourth execute command using the second program; transmitting, by the storage controller and to the second host device, a second latency message based on executing of the fourth execute command. 5 . The computational storage device of claim 4 , wherein: the first host device includes a first virtual machine related to a first tenant, and the second host device includes a second virtual machine related to a second tenant. 6 . The computational storage device of claim 4 , further comprising: storing, by the storage controller, the third execute command in a second command queue; and in response to a latency-related state being: a third state while storing the fourth execute command in the second command queue, storing by the storage controller the fourth execute command in the second command queue, and a fourth state while storing the fourth execute command in the second command queue, transmitting by the storage controller the second latency message to the second host device. 7 . The computational storage device of claim 4 , further comprising: storing, by the storage controller, the third execute command in a second command queue; processing, by a second accelerator, a third computing based on the third execute command; and in response to a latency-related state being: a third state while storing the fourth execute command in the second command queue, storing by the storage controller the fourth execute command in the second command queue, and a fourth state while storing the fourth execute command in the second command queue, transmitting by the storage controller the second latency message to the second host device. 8 . The computational storage device of claim 7 , wherein: the third state is a state in which a sum is equal to or smaller than the second latency threshold value, the sum acquired by adding: a residue time required for the second accelerator to complete the third computing; and a processing time required for the second accelerator to process a fourth computing based on the fourth execute command, and the fourth state is a state in which the sum is greater than the second latency threshold value. 9 . The computational storage device of claim 1 , further comprising: receiving by the storage controller and from a second host device: the first compute namespace setting instruction, a second latency threshold value related to the first compute namespace, and a third execute command using the first program; and transmitting, by the storage controller and to the second host device, a second latency message in response to the third execute command. 10 . The computational storage device of claim 9 , further comprising: in response to a latency-related state being: a third state while storing the third execute command in the first command queue, storing by the storage controller the third execute command in the first command queue, and a fourth state while storing the third execute command in the first command queue, transmitting by the storage controller the second latency message to the second host device. 11 . A method of operating a storage controller, the method comprising: establishing a first compute namespace in response to receiving, from a first host device, a first compute namespace setting instruction; and refusing to accept from the first host device an additional execution command directed to the first compute namespace in response to determining an expected completion time for all uncompleted execution commands accepted by the first compute namespace exceeds a first latency threshold value. 12 . The method of claim 11 , further comprising transmitting a latency message to the first host device informing the first host device the expected completion time exceeds the first latency threshold value. 13 . The method of claim 12 , wherein the latency message informs the first host device to discontinue directing execution commands to the first compute namespace. 14 . The method of claim 11 , wherein the expected completion time for completing all uncompleted execution commands accepted by the first compute namespace is a sum acquired by adding an expected completion time for each of the uncompleted execution commands accepted by the first compute namespace. 15 . The method of claim 11 , further comprising determining whether the expected completion time exceeds the first latency threshold value in response to having received the first latency threshold value from the first host device. 16 . The method of claim 15 , further comprising determining whether the expected completion time exceeds the first latency threshold value in response to each execution command that is received from the first host device and directed to the first compute namespace. 17 . The method of claim 11 , further comprising accepting from a second host device an execution command directed to the first compute namespace in the absence of receiving a second latency threshold value from the second host device. 18 . The method of claim 11 , further comprising accepting fr

Assignees

Inventors

Classifications

  • Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

  • G06F3/0611Primary

    in relation to response time · CPC title

  • Latency reduction · CPC title

  • for peripheral access to main memory, e.g. direct memory access [DMA] · CPC title

  • G06F3/0659Primary

    Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

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What does patent US2025224902A1 cover?
A method for operating a computational storage device includes receiving by a storage controller and from a host device: (1) a compute namespace setting instruction instructing the setting of a compute namespace; (2) a latency threshold value related to the compute namespace; (3) a program; (4) a first execute command using the program; and (5) a second execute command using the program. Additi…
Who is the assignee on this patent?
Samsung Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification G06F3/0611. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Jul 10 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).