Semiconductor memory device and manufacturing method of semiconductor memory device

Patent metadata

Field	Value
Publication number	US-2025220912-A1
Application number	US-202519084414-A
Country	US
Kind code	A1
Filing date	Mar 19, 2025
Priority date	Jun 15, 2021
Publication date	Jul 3, 2025
Grant date	—

Abstract

A semiconductor memory device and a method of manufacturing the semiconductor memory device are provided. The semiconductor memory device includes a gate stacked structure with a cell array region and a contact region with a stepped shape, and a roughness of a first sidewall of the cell array region is greater than that of a second sidewall of the contact region.

First claim

What is claimed is:

1 . A semiconductor memory device, comprising:
a gate stacked structure having a cell array region and a contact region extending from the cell array region; and a plurality of cell plugs passing through the cell array region of the gate stacked structure, wherein the gate stacked structure includes a sinuous sidewall formed by direct connections between curves arranged along the cell array region.

2 . The semiconductor memory device of claim 1 , the curves of the sinuous sidewall are convex toward the plurality of cell plugs.

3 . The semiconductor memory device of claim 1 , the curves of the sinuous sidewall are arranged in one direction.

4 . The semiconductor memory device of claim 1 , wherein the gate stacked structure further includes a straight sidewall formed along the contact region.

5 . The semiconductor memory device of claim 4 , wherein the sinuous sidewall and the straight sidewall are coupled to each other.

6 . The semiconductor memory device of claim 1 , wherein each of the plurality of cell plugs includes:
a channel structure passing through the gate stacked structure; and a memory pattern between the channel structure and the gate stacked structure.

7 . The semiconductor memory device of claim 1 , further comprising:
a conductive source contact adjacent to the sinuous sidewall of the gate stacked structure; and an insulating layer between the conductive source contact and the sinuous sidewall of the gate stacked structure.

8 . The semiconductor memory device of claim 7 , further comprising:
a doped semiconductor layer connected to the conductive source contact and the plurality of cell plugs, wherein the gate stacked structure and the conductive source contact are disposed over the doped semiconductor layer.

9 . The semiconductor memory device of claim 1 , wherein the gate stacked structure includes interlayer insulating layers and conductive patterns that are stacked alternately with each other.

10 . The semiconductor memory device of claim 9 , wherein the interlayer insulating layers and the conductive patterns are penetrated by a slit extending a first direction,
wherein the slit includes a plurality of first auxiliary holes and a plurality of second auxiliary holes adjacent to the first auxiliary holes in a second direction crossing the slit, wherein the plurality of first auxiliary holes are arranged in the first direction and coupled to each other, wherein the plurality of second auxiliary holes are arranged in the first direction, coupled to each other, and coupled to the plurality of first auxiliary holes, and wherein the sinuous sidewall is formed by a connection between the plurality of first auxiliary holes or a connection between the plurality of second auxiliary holes.

11 . The semiconductor memory device of claim 10 , further comprising an insulating layer disposed in the slit.

12 . The semiconductor memory device of claim 10 , further comprising a conductive source contact disposed in the slit.

13 . A semiconductor memory device, comprising:
a first gate stacked structure and a second gate staked structure spaced apart from each other by a slit between the first gate stacked structure and the second gate stacked structure; a plurality of first cell plugs passing through a cell array region of the first gate stacked structure; and a plurality of second cell plugs passing through a cell array region of the second gate stacked structure, wherein the slit includes a sinuous sidewall formed by a direct connection between plurality of auxiliary holes arranged along the cell array region of each of the first and second gate stacked structures.

14 . The semiconductor memory device of claim 13 , wherein the sinuous sidewall is adjacent to the first gate stacked structure and includes a plurality of convex portions toward the plurality of first cell plugs.

15 . The semiconductor memory device of claim 13 , wherein the sinuous sidewall is adjacent to the second gate stacked structure and includes a plurality of convex portions toward the plurality of second cell plugs.

16 . The semiconductor memory device of claim 13 , wherein the plurality of auxiliary holes includes a plurality of first auxiliary holes, and
wherein the plurality of first auxiliary holes are arranged in a first direction in which the slit extends.

17 . The semiconductor memory device of claim 16 , wherein the plurality of auxiliary holes further includes a plurality of second auxiliary holes, and
wherein the plurality of second auxiliary holes are arranged in the first direction and coupled to the plurality of first auxiliary holes in a second direction in which the first gate stacked structure and the second gate stacked structure are spaced apart each other.

18 . The semiconductor memory device of claim 13 , wherein the slit further includes a straight sidewall extending from the sinuous sidewall.

19 . The semiconductor memory device of claim 18 , further comprising a plurality of conductive gate contacts disposed to be adjacent to the straight sidewall and in contact with a contact region of each of the first gate stacked structure and the second gate stacked structure,
wherein the contact region extends from the cell array region of each of the first and second gate stacked structures.

20 . The semiconductor memory device of claim 13 , further comprising:
a conductive source contact disposed in the slit; and a source structure connected to the conductive source contact structure, the plurality of first cell plugs, and the plurality of second cell plugs, wherein the conductive source contact, the first gate stacked structure, and the second gate stacked structure are disposed over the source structure.

21 . The semiconductor memory device of claim 20 , wherein the source structure includes a doped semiconductor layer.

22 . The semiconductor memory device of claim 13 , further comprising an insulating layer disposed in the slit and covering the sinuous sidewall.

23 . The semiconductor memory device of claim 13 , wherein each of the first gate stacked structure and the second gate stacked structure includes interlayer insulating layers and conductive patterns that are stacked alternately with each other.

24 . The semiconductor memory device of claim 23 , wherein each of the plurality of first cell plugs and the plurality of second cell plugs includes:
a channel structure passing through the interlayer insulating layers and the conductive patterns; and a memory pattern surrounding a sidewall of the channel structure.

Assignees

• Sk Hynix Inc

Inventors

• Kim Jang Won
• Park Mi Seong
• Park In Su
• Jang Jung Shik
• Choi Won Geun

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10D84/0149

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title