Semiconductor memory device and manufacturing method of semiconductor memory device

Patent metadata

Field	Value
Publication number	US-2025220911-A1
Application number	US-202519084207-A
Country	US
Kind code	A1
Filing date	Mar 19, 2025
Priority date	Jun 15, 2021
Publication date	Jul 3, 2025
Grant date	—

Abstract

A semiconductor memory device and a method of manufacturing the semiconductor memory device are provided. The semiconductor memory device includes a gate stacked structure with a cell array region and a contact region with a stepped shape, and a roughness of a first sidewall of the cell array region is greater than that of a second sidewall of the contact region.

First claim

What is claimed is:

1 . A method of manufacturing a semiconductor memory device, the method comprising:
forming a stacked structure with a cell array region and a contact region; forming a hole group with a plurality of channel holes and a plurality of auxiliary holes, the plurality of channel holes and the plurality of auxiliary holes passing through the cell array region of the stacked structure and being arranged in a plurality of rows; forming a memory layer along a surface of each of the plurality of channel holes; forming a channel structure on the memory layer; forming a first trench that passes through the contact region of the stacked structure; and removing a part of the stacked structure through the plurality of auxiliary holes and the first trench such that a slit is formed, wherein the plurality of auxiliary holes and the first trench are coupled in the slit.

2 . The method of claim 1 , wherein the plurality of channel holes include a plurality of first channel holes that are arranged along a first row in a first direction and a plurality of second channel holes that are arranged along a second row in the first direction,
wherein the plurality of auxiliary holes include a plurality of first auxiliary holes that are arranged along a third row that is adjacent to the first row in the first direction and a plurality of second auxiliary holes that are arranged along a fourth row that is adjacent to the second row in the first direction, and wherein the third row and the fourth row are disposed between the first row and the second row.

3 . The method of claim 2 , wherein a distance between each of the plurality of first auxiliary holes and each of the plurality of second auxiliary holes is smaller than each of a distance between each of the plurality of first auxiliary holes and each of the plurality of first channel holes and a distance between each of the plurality of second auxiliary holes and each of the plurality of second channel holes.

4 . The method of claim 2 , wherein, in a second direction in which the plurality of rows are arranged, a width of each of the plurality of first and second auxiliary holes is smaller than a width of each of the plurality of first and second channel holes.

5 . The method of claim 1 , wherein a distance between the plurality of auxiliary holes is smaller than a distance between the plurality of channel holes.

6 . The method of claim 1 , wherein, when the first trench is formed, second trenches that pass through the contact region of the stacked structure to be adjacent to both sides of the first trench and a supporting hole that passes through the contact region of the stacked structure between the first trench and the second trench are formed.

7 . The method of claim 6 , further comprising:
forming a supporting pillar that fills the supporting hole and a vertical insulating structure that fills the second trenches; and forming a sacrificial structure that fills the first trench, the sacrificial structure having an etch selectivity with respect to the supporting pillar and the vertical insulating structure.

8 . The method of claim 7 , further comprising,
before the memory layer is formed, forming a first sacrificial pillar that fills each of the plurality of channel holes, forming a second sacrificial pillar that fills each of the plurality of auxiliary holes, and removing the first sacrificial pillar; and after the sacrificial structure is formed, removing the sacrificial structure and the second sacrificial pillar to open the first trench and each of the plurality of auxiliary holes.

9 . The method of claim 1 , wherein the first trench extends straight.

10 . The method of claim 1 , wherein the stacked structure includes first material layers and second material layers that are stacked alternately with each other over a lower structure.

11 . The method of claim 10 , further comprising replacing the second material layers with conductive patterns through the slit.

12 . The method of claim 10 , wherein the lower structure includes a first semiconductor layer, a sacrificial source layer over the first semiconductor layer, a second semiconductor layer over the sacrificial source layer, and an etch stop pattern that passes through the second semiconductor layer, and
wherein the plurality of auxiliary holes and the first trench overlap the etch stop pattern.

13 . The method of claim 12 , further comprising:
removing the etch stop pattern; removing the sacrificial source layer through the slit and a region from which the etch stop pattern is removed; exposing the channel structure by removing a part of the memory layer through a region from which the sacrificial source layer is removed; and filling the region from which the sacrificial source layer is removed with a doped semiconductor layer to contact the channel structure.

Assignees

• Sk Hynix Inc

Inventors

• Kim Jang Won
• Park Mi Seong
• Park In Su
• Jang Jung Shik
• Choi Won Geun

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10D84/0149

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title