Reduce interpolation operations

Patent metadata

Field	Value
Publication number	US-2025217313-A1
Application number	US-202318397757-A
Country	US
Kind code	A1
Filing date	Dec 27, 2023
Priority date	Dec 27, 2023
Publication date	Jul 3, 2025
Grant date	—

Abstract

Apparatuses, methods, and non-transitory computer-readable media are disclosed. One example concerns a reduce interpolation channel-wise instruction to trigger a reduce interpolation channel-wise operation. The reduce interpolation channel-wise operation comprises: selecting a pair of vectors from a range of source vectors in dependence on a first portion of each element of an interpolation vector; a weighted addition of that element from the pair of vectors, wherein a weighting of the weighted addition is dependent on a second portion of that element of the interpolation vector; and storing a result of the weighted addition in that element of a destination vector. Another example concerns a 2D selection instruction to trigger a 2D selection operation comprising, for each vector element: selecting a selected vector from a range of source vectors, wherein the selected vector is selected in dependence on an element value of that element of an index vector; and copying that element from the selected vector of the range of source vectors to that element of a destination vector.

First claim

We claim:

1 . Apparatus comprising:
decoder circuitry responsive to a reduce interpolation channel-wise instruction to generate control signals to trigger a reduce interpolation channel-wise operation, wherein the reduce interpolation channel-wise instruction specifies a range of source vectors, an interpolation vector, and a destination vector, each vector having a number of elements; and processing circuitry responsive to the control signals to perform the reduce interpolation channel-wise operation comprising, for each element of the number of elements: a selection step comprising selecting a pair of vectors from the range of source vectors in dependence on a first portion of that element of the interpolation vector; a weighted addition step comprising performing a weighted addition of that element from the pair of vectors, wherein a weighting of the weighted addition is dependent on a second portion of that element of the interpolation vector; and a storage step comprising storing a result of the weighted addition in that element of the destination vector.

2 . The apparatus as claimed in claim 1 , wherein the first portion of that element of the interpolation vector is an integer portion of that element of the interpolation vector and the second portion of that element of the interpolation vector is a fractional portion of that element of the interpolation vector.

3 . The apparatus as claimed in claim 1 , wherein the weighting of the weighted addition comprises a first weighting applied to a first element from a first vector of the pair of vectors and a second weighting applied to a second element from a second vector of the pair of vectors.

4 . The apparatus as claimed in claim 3 , wherein the first weighting and the second weighting sum to 1.

5 . The apparatus as claimed in claim 1 , wherein the reduce interpolation channel-wise instruction specifies the range of source vectors using a starting source vector and an ending source vector.

6 . The apparatus as claimed in claim 1 , wherein the reduce interpolation channel-wise instruction specifies the range of source vectors using a starting source vector and range value defining a number of vectors in the range of source vectors.

7 . The apparatus as claimed in claim 1 , further comprising issue circuitry configured to issue an instruction to the processing circuitry for execution when an operand defined by the instruction is locally available to the processing circuitry,
wherein the issue circuitry is responsive to the control signals to issue the reduce interpolation channel-wise instruction to the processing circuitry to commence the reduce interpolation channel-wise operation when a first vector of the range of source vectors is locally available.

8 . The apparatus as claimed in claim 1 , wherein the processing circuitry further comprises:
a configurable compute unit to perform parallel arithmetic-logical operations on plural data channels, wherein the configurable compute unit comprises plural processing units to perform the parallel arithmetic-logical operations on the plural data channels; and a complex reduce engine to perform at least some of the reduce interpolation channel-wise operation.

9 . The apparatus as claimed in claim 8 , wherein:
the complex reduce engine is configured to perform the selection step and the configurable compute unit is configured to perform the weighted addition step.

10 . The apparatus as claimed in claim 8 , wherein:
the complex reduce engine is configured to perform the selection step and the weighted addition step.

11 . Apparatus comprising:
decoder circuitry responsive to a 2D selection instruction to generate control signals to trigger a 2D selection operation, wherein the 2D selection instruction specifies a range of source vectors, an index vector, and a destination vector, each vector having a number of elements; and processing circuitry responsive to the control signals to perform the 2D selection operation comprising, for each element of the number of elements: selecting a selected vector of the range of source vectors, wherein the selected vector is selected in dependence on an element value of that element of the index vector; and copying that element from the selected vector of the range of source vectors to that element of the destination vector.

12 . The apparatus as claimed in claim 11 , wherein the 2D selection instruction specifies the range of source vectors using a starting source vector and an ending source vector.

13 . The apparatus as claimed in claim 11 , wherein the 2D selection instruction specifies the range of source vectors using a starting source vector and range value defining a number of vectors in the range of source vectors.

14 . The apparatus as claimed in claim 11 , wherein the decoder circuitry is responsive to a sequence of instructions to generate control signals to trigger a reduce interpolation channel-wise operation, wherein the sequence of instructions comprises:
a preparation set of instructions specifying an interpolation vector, wherein the preparation set of instructions is configured to cause a first index vector and a second index vector to be generated in dependence on an first portion of each element of the interpolation vector and to cause a weighting vector and a complementary weighting vector to be generated in dependence on a second portion of each element of the interpolation vector; a first 2D selection instruction specifying the range of source vectors, the first index vector, and a first destination vector; and a second 2D selection instruction specifying the range of source vectors, the second index vector, and a second destination vector; and a first multiply instruction configured to cause a product of the first destination vector and the weighting vector to be stored in a result vector; and a second multiply accumulate instruction configured to cause a product of the second destination vector and the complementary weighting vector to be accumulated in the result vector.

15 . The apparatus as claimed in claim 14 , wherein the first portion of that element of the interpolation vector is an integer portion of that element of the interpolation vector and the second portion of that element of the interpolation vector is a fractional portion of that element of the interpolation vector.

16 . A method comprising:
operating decoder circuitry which responds to a reduce interpolation channel-wise instruction by generating control signals to trigger a reduce interpolation channel-wise operation, wherein the reduce interpolation channel-wise instruction specifies a range of source vectors, an interpolation vector, and a destination vector, each vector having a number of elements; and operating processing circuitry which responds to the control signals by performing the reduce interpolation channel-wise operation comprising, for each element of the number of elements: a selection step comprising selecting a pair of vectors from the range of source vectors in dependence on a first portion of that element of the interpolation vector; a weighted addition step comprising performing a weighted addition of that element from the pair of vectors, wherein a weighting of the weighted addition is dependent on a second portion of that element of the interpolation vector; and a storage step comprising storing a result of the weighted addition in that element of the destination vector.

17 . A method comprising:
operating decoder circuitry which responds to a 2D selection instruction to generate

Assignees

• Advanced Risc Mach Ltd

Inventors

• VENU Balaji
• Ünal Metin Gokhan
• Gabrielli Giacomo
• Eyole Mbou

Classifications

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F15/8053 Primary

  Vector processors · CPC title

• G06F9/3001 Primary

  Arithmetic instructions · CPC title