Compiler that generates configuration information for configuring an integrated circuit to mitigate inductive-induced voltage droop

Patent metadata

Field	Value
Publication number	US-2025216920-A1
Application number	US-202519081647-A
Country	US
Kind code	A1
Filing date	Mar 17, 2025
Priority date	Sep 9, 2022
Publication date	Jul 3, 2025
Grant date	—

Abstract

A method includes analyzing a dataflow graph to generate configuration information loadable into an integrated circuit. The dataflow graph specifies operations to be performed and data dependencies between the operations. The configuration information is usable by the integrated circuit to configure compute units of the integrated circuit to perform respective one or more of the operations of the dataflow graph, control data flow between the compute units to accomplish the data dependencies between the respective operations performed by the compute units, and control when each compute unit starts to perform the respective operations on the data to mitigate supply voltage droop caused by a time rate of change of current drawn by the integrated circuit through inductive loads of the integrated circuit.

First claim

1 . A method comprising:
analyzing a dataflow graph to generate configuration information loadable into an integrated circuit, wherein the dataflow graph specifies operations to be performed and data dependencies between the operations; and providing the configuration information for use by the integrated circuit to:
configure compute units of the integrated circuit to perform respective one or more of the operations of the dataflow graph;
control data flow between the compute units to accomplish the data dependencies between the respective operations performed by the compute units;
control when each compute unit starts to perform the respective operations on the data to mitigate supply voltage droop caused by a time rate of change of current drawn by the integrated circuit through inductive loads of the integrated circuit;
guarantee that, during execution of the dataflow graph, no more than a predetermined number of compute units concurrently start to perform the respective operations; and
stagger when at least some of the compute units start to perform the respective operations on the data to mitigate the supply voltage droop.

2 . The method of claim 1 , wherein the configuration information is further provided for use by the integrated circuit to:
detect inactivity for a predetermined number of clock cycles by each of the compute units, wherein the staggering when at least some of the compute units start to perform the respective operations is based both on an initial start of execution of the dataflow graph by the integrated circuit and on the inactivity detected subsequent to the initial start of execution of the dataflow graph.

3 . The method of claim 2 ,
wherein the configuration information prioritizes the start of performance of a type of operation that tends to experience the inactivity more often than other types of operations.

4 . The method of claim 1 ,
wherein the stagger is applied to different groups of the compute units concurrently.

5 . A non-transitory computer-readable storage medium storing computer program instructions, wherein the computer program instructions, when executed on a processor, implement a method comprising:
analyzing a dataflow graph to generate configuration information loadable into an integrated circuit, wherein the dataflow graph specifies operations to be performed and data dependencies between the operations; wherein the configuration information is usable by the integrated circuit to:
configure compute units of the integrated circuit to perform respective one or more of the operations of the dataflow graph;
control data flow between the compute units to accomplish the data dependencies between the respective operations performed by the compute units;
control when each compute unit starts to perform the respective operations on the data to mitigate supply voltage droop caused by a time rate of change of current drawn by the integrated circuit through inductive loads of the integrated circuit;
guarantee that a delay of at least a predetermined number of clock cycles intervenes between each instance in which no more than the predetermined number of the compute units concurrently start to perform the respective operations; and
stagger when at least some of the compute units start to perform the respective operations on the data to mitigate the supply voltage droop.

6 . The non-transitory computer readable storage medium of claim 5 , wherein the configuration information is further usable by the integrated circuit to:
detect inactivity for a predetermined number of clock cycles by each of the compute units, wherein the staggering when at least some of the compute units start to perform the respective operations is based both on an initial start of execution of the dataflow graph by the integrated circuit and on the inactivity detected subsequent to the initial start of execution of the dataflow graph.

7 . The non-transitory computer readable storage medium of claim 6 ,
wherein the configuration information prioritizes the start of performance of a type of operation that tends to experience the inactivity more often than other types of operations.

8 . The non-transitory computer readable storage medium of claim 1 ,
wherein the stagger is applied to different groups of the compute units concurrently.

Assignees

• Sambanova Systems Inc

Inventors

• Gandhi Darshan
• Shah Manish K
• Prabhakar Raghu
• Grohoski Gregory Frederick
• Choi Youngmoon
• Shin Jinuk

Classifications

• G06F1/305 Primary

  in the event of power-supply fluctuations · CPC title

• G06F1/3206 Primary

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• G06F1/3243

  Power saving in microcontroller unit · CPC title

• G06F1/3234

  Power saving characterised by the action undertaken · CPC title