Electronic device including interposer

Patent metadata

Field	Value
Publication number	US-2025212331-A1
Application number	US-202519077672-A
Country	US
Kind code	A1
Filing date	Mar 12, 2025
Priority date	Sep 12, 2017
Publication date	Jun 26, 2025
Grant date	—

Abstract

An electronic device including an interposer is provided. The electronic device includes a first circuit board having a first connection terminal formed thereon, an application processor (AP) connected to the first connection terminal and deployed on the first circuit board, an interposer having a via formed therein and having a first surface attached to the first circuit board, the interposer at least partly surrounding at least a partial region of the first circuit board and a first end portion of the via being electrically connected to the first connection terminal, a second circuit board having a second connection terminal formed thereon and attached to a second surface of the interposer in an opposite direction to the first surface, the second connection terminal being electrically connected to a second end portion of the via and the second circuit board forming an inner space together with the first circuit board and the interposer, a communication processor (CP) connected to the second connection terminal and deployed on the second circuit board, and an antenna electrically connected to the CP.

First claim

What is claimed is:

1 . An electronic device comprising:
a first circuit board; a second circuit board; and an interposer connected with the first circuit board and the second circuit board such that an inner space is formed by the first circuit board, the second circuit board and the interposer, the interposer including a lateral outer surface and a lateral inner surface, wherein the lateral outer surface of a portion of the interposer includes a first plating region, a second plating region and a first non-plating region located between the first plating region and the second plating region, wherein a plating region is disposed at the lateral inner surface of the interposer to overlap with the first non-plating region of the lateral outer surface when viewed from a direction substantially perpendicular to the lateral outer surface and the lateral inner surface.

2 . The electronic device of claim 1 , wherein the plating region disposed at the lateral inner surface of the interposer overlaps with a substantially entire length of the first non-plating region of the lateral outer surface when viewed from a direction substantially perpendicular to the lateral outer surface and the lateral inner surface.

3 . The electronic device of claim 1 , wherein the interposer includes a via formed between the first non-plating region and the plating region.

4 . The electronic device of claim 3 , wherein the plating region is electrically connected with the via.

5 . The electronic device of claim 3 , wherein the plating region is connected to a ground region.

6 . The electronic device of claim 1 , wherein the interposer further includes a second non-plating region located adjacent to the plating region.

7 . The electronic device of claim 6 , wherein a substantially entire length of the second non-plating region is overlapped with the first plating region or the second plating region when viewed from the direction.

8 . The electronic device of claim 1 , wherein the first circuit board includes an application processor and a communication processor disposed thereon.

9 . The electronic device of claim 1 , wherein the second circuit board includes a transceiver disposed thereon.

10 . The electronic device of claim 8 ,
wherein the application processor is disposed inside of the inner space, and wherein the communication processor is disposed outside of the inner space.

11 . The electronic device of claim 8 , wherein the first circuit board further includes a first shield can disposed outside of the inner space and enclosing the communication processor.

12 . The electronic device of claim 9 , wherein the second circuit board further includes a second shield can disposed outside of the inner space and enclosing the transceiver.

13 . The electronic device of claim 1 , wherein the interposer is separated through at least one slit.

14 . The electronic device of claim 1 , wherein the interposer further includes a via and a ground region surrounding at least a portion of the via.

15 . The electronic device of claim 14 , wherein the via includes:
a hole penetrating at least a portion of the interposer; a plating pad surrounding at least a portion of the hole; and an insulation region surrounding at least a portion of the plating pad.

16 . The electronic device of claim 14 , wherein the via includes:
an inner via configured to transfer an electrical signal; a plating pad surrounding at least a part of the inner via; and an insulation region surrounding at least a part of the plating pad.

17 . The electronic device of claim 14 , wherein the first plating region and the via are electrically connected to each other through an interconnect.

18 . The electronic device of claim 14 , wherein the first plating region is connected to the ground region through an extension part extending from the ground region.

19 . The electronic device of claim 9 , wherein the second circuit board further includes an antenna.

20 . The electronic device of claim 19 , wherein the antenna includes an antenna array to be used for forming a beam corresponding to millimeter (mm) wave communication.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Jungsik
• Lee Soyoung

Classifications

• H05K2201/10378

  Interposers · CPC title

• H05K2201/10189

  Non-printed connector · CPC title

• H05K2201/10098

  Components for radio transmission, e.g. radio frequency identification [RFID] tag, printed or non-printed antennas · CPC title

• H05K2201/10037

  Printed or non-printed battery · CPC title

• H05K2201/042

  Stacked spaced PCBs; Planar parts of folded flexible circuits having mounted components in between or spaced from each other · CPC title