Light load efficiency boost for switched capacitor power converters

Patent metadata

Field	Value
Publication number	US-2025211085-A1
Application number	US-202318394927-A
Country	US
Kind code	A1
Filing date	Dec 22, 2023
Priority date	Dec 22, 2023
Publication date	Jun 26, 2025
Grant date	—

Abstract

Embodiments herein relate to a switched capacitor power converter which reduces the leakage current through a power switch when the power switch is turned off. In one aspect, a first charge pump provides a voltage Vcc_cp which is higher than a power supply voltage Vcc, and a second charge pump provides a voltage Vss_cp which is lower than a ground voltage Vss. Transistors are used to couple the first charge pump to the control gate of a p-type power switch and to couple the second charge pump to the control gate of an n-type power switch. In another example implementation, the voltage of the power switch is pulled up or down using a bootstrap capacitor.

First claim

What is claimed is:

1 . An apparatus, comprising:
a power switch among a plurality of power switches which are coupled to a capacitor; a driver coupled to a control gate of the power switch, wherein the driver has a power supply terminal and a ground terminal; a first transistor coupled between the power supply terminal and a node; a charge pump; and a second transistor coupled between the control gate of the power switch and the charge pump.

2 . The apparatus of claim 1 , wherein the power switch is a first power switch, the charge pump is a first charge pump, and the apparatus further comprises:
a second power switch coupled to the capacitor; a second charge pump; and a third transistor coupled between a control gate of the second power switch and the second charge pump.

3 . The apparatus of claim 1 , wherein:
the capacitor is a charge transfer component in a switched capacitor voltage converter; and the power switch is a p-type input power switch of the switched capacitor voltage converter or the power switch is an n-type output power switch of the switched capacitor voltage converter.

4 . The apparatus of claim 1 , wherein:
the capacitor is a charge transfer component in a switched capacitor voltage converter; each power switch of the plurality of power switches is coupled between a respective voltage rail and the capacitor; and each respective voltage rail is to provide a voltage at a different level.

5 . The apparatus of claim 1 , further comprising a third transistor coupled between the ground terminal and a ground node, wherein the third transistor is to turn on to couple the ground terminal to the ground node.

6 . The apparatus of claim 1 , wherein:
the driver is to apply a turn off voltage to the control gate of the power switch while another power switch of the plurality of power switches is turned on; and during the applying of the turn off voltage to the control gate of the power switch, the first transistor is to receive a control gate voltage to turn off and block the power supply terminal from the node and the second transistor is to receive a control gate voltage to turn on to couple the control gate of the power switch to the charge pump.

7 . The apparatus of claim 1 , wherein a turn off of the first transistor and a turn on of the second transistor are started after a start of the driver applying a turn off voltage to the power switch.

8 . The apparatus of claim 1 , wherein the node is a ground node and when the second transistor is turned on, the charge pump is to decrease a voltage of the control gate of the power switch from a voltage of the ground node to a voltage which is output by the charge pump.

9 . The apparatus of claim 1 , wherein the node is a power supply node and when the second transistor is turned on, the charge pump is to increase a voltage of the control gate of the power switch from a voltage of the power supply node to a voltage which is output by the charge pump.

10 . The apparatus of claim 9 , wherein the voltage which is output by the charge pump provides a greater leakage protection for the power switch compared to the voltage of the power supply node.

11 . The apparatus of claim 1 , further comprising a switched capacitor voltage converter which includes the plurality of power switches, the capacitor, the driver, the first transistor, the charge pump and the second transistor, wherein the switched capacitor voltage converter is provided in at least one of an integrated circuit, a System on Chip, a System in Package or a computing device.

12 . An apparatus, comprising:
a first transistor in series with a second transistor, wherein the first transistor is coupled to a power supply node; a power switch having a control gate coupled to a node between the first transistor and the second transistor; a bootstrap capacitor coupled to the control gate of the power switch, wherein the bootstrap capacitor is to receive a clock signal; a logic circuit coupled to a control gate of the first transistor; and a driver coupled to the logic circuit and to a control gate of the second transistor.

13 . The apparatus of claim 12 , wherein:
the power switch comprises a p-type transistor; in response to a transition in an output of the driver, the logic circuit is to turn on the first transistor to increase a voltage of the control gate of the power switch to a voltage of the power supply node; and the clock signal is to decrease and then increase, to increase the voltage of the control gate of the power switch higher than the voltage of the power supply node based on a voltage across the bootstrap capacitor.

14 . The apparatus of claim 13 , wherein:
the logic circuit is to turn on the first transistor for a first time period; and the decrease and increase of the clock is in a second time period which starts after a start of the first time period and ends after an end of the first time period.

15 . The apparatus of claim 13 , wherein the turn on of the first transistor and the decrease and then increase of the clock occur multiple times after a single transition of the output of the driver.

16 . An apparatus, comprising:
a memory to store instructions; and a control circuit to execute the instructions to:
apply a control gate voltage at a turn on level to one selected power switch at a time among a first plurality of power switches to couple a respective voltage rail of the selected power switch to a capacitor in a switched capacitor voltage converter, wherein each power switch of the first plurality of power switches is coupled between the respective voltage rail and to the capacitor; and
apply control gates voltages at a first turn off level and then at a second turn off level to unselected power switches of the first plurality of power switches during the applying of the control gate voltage at the turn on level to the one selected power switch, wherein when the unselected power switches comprise n-type transistors, the first turn off level is less than the second turn off level, and when the unselected power switches comprise p-type transistors, the first turn off level is greater than the second turn off level.

17 . The apparatus of claim 16 , wherein:
the first plurality of power switches are in a power switch circuit; when a load current of the switched capacitor voltage converter is below a lower threshold, the control circuit is to execute the instructions to turn off, and park in an anti-leakage mode, a portion of all power switches in the power switch circuit; and when the load current is above an upper threshold, the control circuit is to execute the instructions to turn on all of the power switches of the power switch circuit.

18 . The apparatus of claim 16 , wherein:
each power switch of the first plurality of power switches comprises a respective driver coupled to a control gate of the power switch; the respective driver comprises a power supply terminal coupled to a power supply node; the control gate of the power switch is coupled to a respective charge pump; and the first turn off level is based on a level of the power supply node and the second turn off level is based on a level of the respective charge pump, which is greater than the level of the power supply node.

19 . The apparatus of claim 16 , wherein:
each power switch of the first plurality of power switches comprises a respective driver coupled to a control gate of the power switch; the respective driver comprises a ground terminal coupled to a

Assignees

• Intel Corp

Inventors

• Zhang Huanhuan
• Raghavan Arvind
• Schaef Christopher
• Chen Keng
• Masilamani Sivaraman
• Kocharyan Yura

Classifications

• H02M3/07

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H02M1/0032 Primary

  Control circuits allowing low power mode operation, e.g. in standby mode · CPC title

• H02M1/0048

  Circuits or arrangements for reducing losses (using snubbers H02M1/34) · CPC title

• H02M1/0006

  Arrangements for supplying an adequate voltage to the control circuit of converters · CPC title

• H02M3/158 Primary

  including plural semiconductor devices as final control devices for a single load · CPC title