Layout designing method and integrated circuit device manufacturing method using the same

Patent metadata

Field	Value
Publication number	US-2025209247-A1
Application number	US-202418981969-A
Country	US
Kind code	A1
Filing date	Dec 16, 2024
Priority date	Dec 22, 2023
Publication date	Jun 26, 2025
Grant date	—

Abstract

A method for layout designing, includes preparing a first layout, forming a test pattern based on the first layout generating first error data based on the first layout and the test pattern, wherein the first error data includes a value of misalignment of the test pattern from a reference position, normalizing coordinate data of the first layout to obtain first coordinate data, generating first stress distribution data by performing finite element analysis simulation, wherein a boundary condition of the structural analysis mesh model is determined based on the first coordinate data, generating an error prediction machine learning model based on the first error data, the first coordinate data, and the first stress distribution data, predicting second error data of a second layout, and generating a final layout based on the second error data.

First claim

What is claimed is:

1 . A method for layout designing, comprising:
preparing a first layout; forming a test pattern based on the first layout; generating first error data based on the first layout and the test pattern, wherein the first error data includes a value of misalignment of the test pattern from a reference position; normalizing coordinate data of the first layout to obtain first coordinate data; generating, using a structural analysis mesh model, first stress distribution data by performing finite element analysis simulation, wherein a boundary condition of the structural analysis mesh model is determined based on the first coordinate data; generating an error prediction machine learning model based on the first error data, the first coordinate data, and the first stress distribution data; predicting, using the error prediction machine learning model, second error data of a second layout, wherein the second layout is different from the first layout; and generating a final layout based on the second error data.

2 . The layout designing method of claim 1 , wherein predicting the second error data comprises:
normalizing coordinate data of the second layout to obtain second coordinate data; generating, using the structural analysis mesh model, second stress distribution data by performing a finite element analysis simulation, wherein the boundary condition of the structural analysis mesh model is determined based on the second coordinate data; and generating, using the error prediction machine learning model, the second error data based on the second coordinate data and the second stress distribution data.

3 . The layout designing method of claim 2 , wherein the first coordinate data and the second coordinate data are normalized to a same dimension.

4 . The layout designing method of claim 1 , wherein generating the final layout comprises:
computing a correction value based on the second error data; and combining the correction value to the second layout.

5 . The layout designing method of claim 1 , wherein generating the error prediction machine learning model comprises:
performing a Gaussian process regression (GPR) using a multi-kernel function.

6 . The layout designing method of claim 5 , wherein generating the error prediction machine learning model comprises:
performing multi-kernel parameter optimization using a maximum likelihood estimation (MLE).

7 . The layout designing method of claim 6 , wherein the multi-kernel parameter optimization comprises:
iteratively performing multi-kernel parameter optimization based on an optimization score.

8 . The layout designing method of claim 1 , wherein the first error data further comprises:
a first error value of misalignment between the test pattern and the reference position in a first direction; and a second error value of misalignment between the test pattern and the reference position in a second direction, wherein the second direction is perpendicular to the first direction.

9 . The layout designing method of claim 8 , wherein the first stress distribution data includes a first stress value measured in the first direction and a second stress value measured in the second direction.

10 . The layout designing method of claim 1 , wherein forming the test pattern comprises:
forming a test mold structure pattern including one or more test holes; forming one or more test lower electrodes in the one or more test holes; and forming one or more test opening patterns penetrating the test mold structure pattern to expose at least a portion of a side surface of the one or more test lower electrodes.

11 . The layout designing method of claim 10 , wherein the reference position is a distance between a center of each of the one or more test opening patterns and a center of a virtual polygon formed from centers of upper surfaces of three or more test lower electrodes adjacent to the center of each of the one or more test opening patterns.

12 . The layout designing method of claim 11 , wherein the first error data includes a position difference between the center of each of the one or more test opening patterns and the center of the virtual polygon.

13 . A method for layout designing, comprising:
obtaining data on a test pattern formed based on a first layout; generating, using a first error data extracting module, first error data based on the first layout and the test pattern, wherein the first error data is a value of misalignment of the test pattern from a reference position; normalizing, using a first coordinate data extracting module, the coordinate information of the first layout to a target dimension to obtain first coordinate data; generating, using a first stress distribution data extracting module, first stress distribution data by performing finite element simulation analysis, wherein a boundary condition of the first stress distribution data extracting module is determined based on the first coordinate data; generating, using an error prediction machine learning model generating module, an error prediction machine learning model based on the first error data, the first coordinate data, and the first stress distribution data; generating, using a second coordinate data extracting module, second coordinate data based on coordinate information of a second layout and normalizing the coordinate information of the second layout to the target dimension, wherein the second layout is different from the first layout; generating, using a second stress distribution data extracting module, second stress distribution data by performing finite element simulation analysis, wherein a boundary condition of the second stress distribution data extracting module is determined based on the second coordinate data; and predicting, using a second error data predicting module, second error data of the second layout based on the second coordinate data and the second stress distribution data.

14 . The layout designing method of claim 13 , wherein generating the error prediction machine learning model comprises:
performing, using the error prediction machine learning model generating module, a Gaussian process regression (GPR) using a multi-kernel function; and performing multi-kernel parameter optimization using a maximum likelihood estimation (MLE).

15 . A method for manufacturing an integrated circuit device, comprising:
disposing a mold structure on a substrate; penetrating the mold structure to obtain a plurality of holes; forming a plurality of lower electrodes filling the plurality of holes; forming a plurality of opening patterns penetrating the mold structure in a third direction perpendicular to the substrate based on a final layout of a layout design; forming a dielectric layer covering the plurality of opening patterns; and forming an upper electrode filling the plurality of opening patterns on the dielectric layer, wherein the layout design comprises: constructing an error prediction machine learning model by performing a finite element analysis simulation on a first layout; and generating, using the error prediction machine learning model, the final layout based on a second layout, wherein the second layout is different from the first layout.

16 . The method for manufacturing the integrated circuit device of claim 15 , wherein constructing the error prediction machine learning model comprises:
forming a test pattern based on the first layout; generating first error data based on the test pattern, wherein the first error data includes a value of misalignment of the t

Assignees

• Samsung Electronics Co Ltd

Inventors

• Chung Ingyun
• Park Dongjin

Classifications

• G06F2117/12

  Sizing, e.g. of transistors or gates · CPC title

• G06F2119/02

  Reliability analysis or reliability optimisation; Failure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA] · CPC title

• G06N20/00

  Machine learning · CPC title

• H10B12/01

  Manufacture or treatment · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title