Systems and methods that include standard cell yield predictions in a library

Patent metadata

Field	Value
Publication number	US-2025209221-A1
Application number	US-202318394596-A
Country	US
Kind code	A1
Filing date	Dec 22, 2023
Priority date	Dec 22, 2023
Publication date	Jun 26, 2025
Grant date	—

Abstract

Systems and methods for providing standard cell yield information in a library (i.e., creating “defect-aware” libraries). The method includes accessing a library of a plurality of standard cells characterized on a foundry process node and revision. A geometric analysis is performed on individual ones of the standard cells to identify potential defects, such as shorts and opens. A defect is injected (i.e., “realized” or “actualized”) at the location of the identified potential defects. The standard cells in the library are then simulated with the defects injected to generate simulated yield information. Additionally, methods can access silicon failure analysis data representing test chips designed with the library and generate an inferred failure rate for the individual standard cells in the library, as a function of the silicon failure analysis and the simulated yield information.

First claim

What is claimed is:

1 . A method comprising:
accessing a library comprising a plurality of standard cells, wherein the library is characterized on a foundry process node and process node revision; for individual ones of the plurality of standard cells, performing a geometric analysis on said individual ones of the plurality of standard cells; identifying one or more potential defects based on the geometric analysis; in response to determining a potential defect in an individual standard cell, identifying the individual standard cell as a potentially defective standard cell and implementing a defect injection process; and generating simulated yield information for the library on the foundry process node and the process node revision based on implementation of the defect injection process.

2 . The method of claim 1 , further comprising:
accessing silicon failure analysis data representing a plurality of test chips designed with the library; and generating an inferred failure rate for the individual standard cells of the plurality of standard cells, as a function of the silicon failure analysis and the simulated yield information.

3 . The method of claim 2 , further comprising:
accessing new silicon failure analysis data representing a different plurality of test chips designed with the library; and revising the inferred failure rate for the individual standard cells of the plurality of standard cells based at least in part on the new silicon failure analysis data.

4 . The method of claim 3 , wherein revising the simulated yield information is performed by a machine learning model.

5 . The method of claim 2 , wherein the library is a first library, the process node revision is a first process node revision, and further comprising:
accessing a second library comprising the plurality of standard cells, wherein the second library is characterized on the foundry process node and a second process node revision; and generating a second inferred failure rate for the individual standard cells in the second library based at least in part on the inferred failure rate.

6 . The method of claim 2 , wherein the library is a first library, the foundry process node is a first foundry process node, the process node revision is a first process node revision, and further comprising:
accessing a second library comprising the plurality of standard cells, wherein the second library is characterized on a second foundry process node and a second process node revision; and generating a second inferred failure rate for the individual standard cells in the second library based at least in part on the inferred failure rate.

7 . The method of claim 1 , wherein potential defects comprise opens and shorts.

8 . The method of claim 1 , wherein performing the geometric analysis comprises processing layout and margin information identify locations that are vulnerable to an open or a short.

9 . The method of claim 1 , wherein implementing the defect injection process comprises revising the potentially defective standard cell to include an open or a short.

10 . An apparatus, comprising:
circuitry to:
reference a library comprising a plurality of standard cells;
create a synthesized product chip based on the library; and
wherein the library is characterized on a foundry process node and process node revision;
wherein the synthesized product chip reflects simulated yield information for the library on the foundry process node and the process node revision based on implementation of a defect injection process.

11 . The apparatus of claim 10 , wherein the circuitry is further to:
for individual ones of the plurality of standard cells, perform a geometric analysis on said individual ones of the plurality of standard cells; identify one or more potential defects based on the geometric analysis; in response to determining a potential defect in an individual standard cell, identify the individual standard cell as a potentially defective standard cell and implement a defect injection process; and generate the simulated yield information for the library on the foundry process node and the process node revision based on the defect injection process.

12 . The apparatus of claim 10 , wherein the circuitry is further to:
access silicon failure analysis data representing a plurality of test chips designed with the library; and generate an inferred failure rate for individual standard cells of the plurality of standard cells, as a function of the silicon failure analysis and the simulated yield information.

13 . The apparatus of claim 12 , wherein the circuitry is further to:
access new silicon failure analysis data representing a different plurality of test chips designed with the library; and revise the inferred failure rate for the individual standard cells of the plurality of standard cells based at least in part on the new silicon failure analysis data.

14 . One or more computer-readable storage media storing computer-executable instructions which when executed by a processor cause the processor to perform a method, the method comprising:
accessing a library comprising a plurality of standard cells, wherein the library is characterized on a foundry process node and process node revision; for individual ones of the plurality of standard cells, performing a geometric analysis on said individual ones of the plurality of standard cells; identifying one or more potential defects based on the geometric analysis; in response to determining a potential defect in an individual standard cell, identifying the individual standard cell as a potentially defective standard cell and implementing a defect injection process; and generating simulated yield information for the library on the foundry process node and the process node revision based on implementation of the defect injection process.

15 . The one or more computer-readable storage media of claim 14 , wherein the method further comprises:
accessing silicon failure analysis data representing a plurality of test chips designed with the library; and generating an inferred failure rate for the individual standard cells of the plurality of standard cells, as a function of the silicon failure analysis and the simulated yield information.

16 . The one or more computer-readable storage media of claim 15 , wherein the method further comprises:
accessing new silicon failure analysis data representing a different plurality of test chips designed with the library; and revising the inferred failure rate for the individual standard cells of the plurality of standard cells based at least in part on the new silicon failure analysis data.

17 . The one or more computer-readable storage media of claim 16 , wherein revising the simulated yield information is performed by a machine learning model.

18 . The one or more computer-readable storage media of claim 15 , wherein the library is a first library, the process node revision is a first process node revision, and wherein the method further comprises:
accessing a second library comprising the plurality of standard cells, wherein the second library is characterized on the foundry process node and a second process node revision; and generating a second inferred failure rate for the individual standard cells in the second library based at least in part on the inferred failure rate.

19 . The one or more computer-readable storage media of claim 15 , wherein the library is a first library, the foundry process node is a first

Assignees

• Intel Corp

Inventors

• Raman Srikanth Venkat
• Meinerzhagen Pascal A
• Radcliffe Andrew
• Liu Jimmy Voong
• Gandhi Jay
• Khellah Muhammad M

Classifications

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/27

  using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model · CPC title

• G06F30/10 Primary

  Geometric CAD · CPC title