Display apparatus

Patent metadata

Field	Value
Publication number	US-2025204151-A1
Application number	US-202418806699-A
Country	US
Kind code	A1
Filing date	Aug 16, 2024
Priority date	Dec 19, 2023
Publication date	Jun 19, 2025
Grant date	—

Abstract

A display apparatus is disclosed that includes a substrate, a first thin-film transistor, a second thin-film transistor, and a lower conductive layer. The first thin-film transistor is located on the substrate and includes a first semiconductor layer and a first gate electrode. The second thin-film transistor is located on the substrate and includes a second semiconductor layer, a second gate electrode, a lower electrode, and an upper electrode. The lower conductive layer is located between the substrate and the first semiconductor layer. A first angle between a channel region of the first semiconductor layer and the substrate is different from a second angle between a channel region of the second semiconductor layer and the substrate. The first gate electrode and the second gate electrode are located on a same layer.

First claim

What is claimed is:

1 . A display apparatus comprising:
a substrate; a first thin-film transistor located on the substrate and comprising a first semiconductor layer and a first gate electrode; a second thin-film transistor located on the substrate and comprising a second semiconductor layer, a second gate electrode, a lower electrode, and an upper electrode; and a lower conductive layer located between the substrate and the first semiconductor layer, wherein a first angle between a channel region of the first semiconductor layer and the substrate is different from a second angle between a channel region of the second semiconductor layer and the substrate, wherein the first gate electrode and the second gate electrode are located on a same layer, and the lower electrode and the lower conductive layer are located on a same layer.

2 . The display apparatus of claim 1 , wherein the first angle is 0° to 5°, and the second angle is 20° to 90°.

3 . The display apparatus of claim 1 , wherein the lower electrode of the second thin-film transistor is connected to the lower conductive layer.

4 . The display apparatus of claim 3 , wherein a central portion of the second semiconductor layer is connected to the lower electrode, and a peripheral portion of the second semiconductor layer is connected to the upper electrode.

5 . The display apparatus of claim 3 , further comprising a first insulating layer located between the lower electrode and the upper electrode,
wherein the first insulating layer comprises a first opening that extends to the lower electrode, and at least a part of the second semiconductor layer is located in the first opening.

6 . The display apparatus of claim 5 , further comprising a second insulating layer covering the second semiconductor layer,
wherein a thickness of the second insulating layer is less than a thickness of the first insulating layer.

7 . The display apparatus of claim 1 , further comprising a storage capacitor comprising a first capacitor electrode and a second capacitor electrode,
wherein the first capacitor electrode is located on a same layer as the first gate electrode and the second gate electrode.

8 . The display apparatus of claim 1 , wherein each of the first semiconductor layer and the second semiconductor layer comprises an oxide semiconductor.

9 . The display apparatus of claim 1 , further comprising a third thin-film transistor located on the substrate and comprising a third semiconductor layer and a third gate electrode,
wherein each of the first semiconductor layer and the second semiconductor layer comprises an oxide semiconductor, and the third semiconductor layer comprises a silicon semiconductor.

10 . The display apparatus of claim 9 , wherein the third gate electrode is located above the third semiconductor layer and below a first insulating layer, and
the first semiconductor layer is located above the first insulating layer.

11 . A display apparatus comprising:
a substrate; a first insulating layer located on the substrate and comprising a first opening; a first thin-film transistor comprising a first semiconductor layer and a first gate electrode, the first semiconductor layer being located on a top surface of the first insulating layer; a second thin-film transistor comprising a second semiconductor layer at least partially located in the first opening, a lower electrode located under the first insulating layer, an upper electrode located over the first insulating layer, and a second gate electrode located on the second semiconductor layer; and a second insulating layer covering the first semiconductor layer and the second semiconductor layer, wherein the first gate electrode and the second gate electrode are located on the second insulating layer.

12 . The display apparatus of claim 11 , wherein an angle between an inner wall of the first opening and a top surface of the substrate is 20° to 90°.

13 . The display apparatus of claim 11 , further comprising a lower conductive layer located between the substrate and the first semiconductor layer,
wherein the lower electrode is located on a same layer as the lower conductive layer.

14 . The display apparatus of claim 11 , wherein a central portion of the second semiconductor layer is connected to the lower electrode, and a peripheral portion of the second semiconductor layer is connected to the upper electrode.

15 . The display apparatus of claim 11 , wherein a thickness of the second insulating layer is less than a thickness of the first insulating layer.

16 . The display apparatus of claim 11 , wherein each of the first semiconductor layer and the second semiconductor layer comprises an oxide semiconductor.

17 . The display apparatus of claim 11 , further comprising a storage capacitor comprising a first capacitor electrode and a second capacitor electrode,
wherein the first capacitor electrode is located on a same layer as the first gate electrode and the second gate electrode.

18 . The display apparatus of claim 11 , further comprising a third thin-film transistor located on the substrate and comprising a third semiconductor layer and a third gate electrode,
wherein each of the first semiconductor layer and the second semiconductor layer comprises an oxide semiconductor, and the third semiconductor layer comprises a silicon semiconductor.

19 . The display apparatus of claim 18 , wherein the third gate electrode is located above the third semiconductor layer and below a first insulating layer, and
the first semiconductor layer is located above the first insulating layer.

20 . The display apparatus of claim 11 , wherein the substrate comprises a display area and a peripheral area around the display area,
wherein the display apparatus further comprises a built-in driving thin-film transistor located in the peripheral area, wherein the built-in driving thin-film transistor is a vertical-type thin-film transistor.

Assignees

• Samsung Display Co Ltd

Inventors

• SON Kyoungseok
• Kim Youngoo
• Kim Jaybum
• Lee Seunghun

Classifications

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D30/6728

  Vertical TFTs · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/471

  having different architectures, e.g. having both top-gate and bottom-gate TFTs · CPC title

• H10K59/12

  Active-matrix OLED [AMOLED] displays · CPC title