Circuit board and semiconductor package comprising same

Patent metadata

Field	Value
Publication number	US-2025203761-A1
Application number	US-202218712570-A
Country	US
Kind code	A1
Filing date	Nov 23, 2022
Priority date	Nov 23, 2021
Publication date	Jun 19, 2025
Grant date	—

Abstract

A circuit board according to an embodiment includes a first insulating layer; a second insulating layer disposed on the first insulating layer; a first electrode part disposed on the second insulating layer; a second electrode part disposed on the first electrode part; a second insulating layer disposed on the second electrode part; and a fourth insulating layer disposed on the third insulating layer, wherein an upper surface of the first insulating layer includes a plurality of first convex parts, wherein a lower surface of the fourth insulating layer includes a plurality of second convex parts, and wherein at least one of distances between adjacent first convex parts among the plurality of first convex parts includes a region different from at least one of distances between adjacent second convex parts among the plurality of second convex parts.

First claim

1 . A circuit board comprising:
a first insulating layer; a second insulating layer disposed on the first insulating layer; a first electrode part disposed on the second insulating layer; a second electrode part disposed on the first electrode part; a third insulating layer disposed on the second electrode part; and a fourth insulating layer disposed on the third insulating layer, wherein an upper surface of the first insulating layer includes a plurality of first convex parts, wherein a lower surface of the fourth insulating layer includes a plurality of second convex parts, and wherein at least one of distances between adjacent first convex parts among the plurality of first convex parts includes a region different from at least one of distances between adjacent second convex parts among the plurality of second convex parts.

2 . The circuit board of claim 1 , wherein the first convex part is convex toward the first electrode part, and
wherein the second convex part is convex toward the second electrode part.

3 . The circuit board of claim 1 , wherein the first electrode part includes a plurality of first electrodes spaced apart from each other along a horizontal direction, and
wherein the second electrode part includes a plurality of second electrodes spaced apart from each other along the horizontal direction, wherein the plurality of first convex parts vertically overlap at least one of the plurality of second electrodes, and wherein the plurality of second convex parts vertically overlap at least one of the plurality of first electrodes.

4 . The circuit board of claim 3 , wherein each of the plurality of first convex parts is positioned between the plurality of first electrodes, and
wherein each of the plurality of second convex parts is positioned between the plurality of second electrodes.

5 . The circuit board of claim 1 , wherein the second insulating layer and the third insulating layer do not include glass fibers, and
wherein the first insulating layer and the fourth insulating layer include glass fibers.

6 . The circuit board of claim 1 , wherein each of the first to fourth insulating layers includes a filler,
wherein a filler content of the first insulating layer is higher than that of the second insulating layer, and wherein a filler content of the fourth insulating layer is higher than that of the third insulating layer.

7 . The circuit board of claim 1 , further comprising:
an insulating substrate disposed between the first electrode part and the second electrode part.

8 . The circuit board of claim 1 , further comprising:
a third electrode part disposed under the first insulating layer; and a fourth electrode part disposed on the fourth insulating layer.

9 . The circuit board of claim 8 , further comprising:
a first through part disposed in the first insulating layer and the second insulating layer; and a second through part disposed in the third insulating layer and the fourth insulating layer, wherein the first through part connects the first electrode part and the third electrode part, and wherein the second through part connects the fourth electrode part and the second electrode part.

10 . The circuit board of claim 9 , wherein the first through part includes:
a first-first part passing through the first insulating layer and having a first slope whose width gradually decreases toward the upper surface of the first insulating layer; and a first-second part passing through the second insulating layer and having a second slope different from the first slope whose width gradually decreases toward the upper surface of the second insulating layer.

11 . The circuit board of claim 10 , wherein an interior angle between a lower surface of the first through part and the first slope is smaller than an interior angle between the lower surface of the first through part and the second slope.

12 . The circuit board of claim 9 , wherein the second through part includes:
a second-first part passing through the third insulating layer and having a third slope whose width gradually increases toward an upper surface of the third insulating layer; and a second-second part passing through the fourth insulating layer and having a fourth slope different from the third slope whose width gradually increases toward the upper surface of the fourth insulating layer.

13 . The circuit board of claim 12 , wherein an interior angle between a lower surface of the second through part and the third slope is smaller than an interior angle between the lower surface of the second through part and the fourth slope.

14 . The circuit board of claim 1 , wherein a lower surface of the first insulating layer includes a region in which a height changes to correspond to the plurality of first convex parts, and
wherein an uppermost end of the lower surface of the first insulating layer is positioned lower than a lower surface of the first electrode part.

15 . The circuit board of claim 8 , wherein the second insulating layer includes:
a second-first insulating layer disposed on the first insulating layer; and a second-second insulating layer disposed under the first insulating layer, wherein the first electrode part is disposed on the second-first insulating layer, and wherein the third electrode part is disposed under the second-second insulating layer.

16 . The circuit board of claim 8 , wherein the third insulating layer includes:
a third-first insulating layer disposed under the fourth insulating layer; and a third-second insulating layer disposed on the fourth insulating layer, wherein the second electrode part is disposed under the third-first insulating layer, and wherein the fourth electrode part is disposed on the third-second insulating layer.

17 . The circuit board of claim 1 , wherein an upper surface of the third insulating layer includes a region in which a height changes to correspond to the plurality of second convex parts, and
wherein a lowermost end of the upper surface of the third insulating layer is positioned higher than an upper surface of the second electrode part.

18 . A semiconductor package substrate comprising:
a first insulating layer; a second insulating layer disposed on the first insulating layer; a first electrode part disposed on the second insulating layer; a second electrode part disposed on the first electrode part; a third insulating layer disposed on the second electrode part; a fourth insulating layer disposed on the third insulating layer; a third electrode part disposed under the first insulating layer; a fourth electrode part disposed on the fourth insulating layer; a connection part disposed on at least one of a plurality of fourth electrodes of the fourth electrode part; and a chip mounted on the connection part, wherein an upper surface of the first insulating layer includes a plurality of first convex parts, wherein a lower surface of the fourth insulating layer includes a plurality of second convex parts, wherein a least one of distances between the first convex parts adjacent to each other among the plurality of first convex parts includes a region different from at least one of the distances between the second convex parts adjacent to each other among the plurality of second convex parts.

19 . The semiconductor package substrate of claim 18 , wherein the first convex part is convex toward the first electrode part, and
wherein the second convex part is convex toward the second electrode part.

Assignees

• Lg Innotek Co Ltd

Inventors

• Park Duck Hoon
• Kim Hae Sik
• Paik Jee Heum

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H05K1/112

  directly combined with via connections · CPC title

• H05K1/181

  associated with surface mounted components · CPC title

• H05K2201/096

  Vertically aligned vias, holes or stacked vias · CPC title