Memory device and operating method of the memory device

Patent metadata

Field	Value
Publication number	US-2025201315-A1
Application number	US-202418670841-A
Country	US
Kind code	A1
Filing date	May 22, 2024
Priority date	Dec 14, 2023
Publication date	Jun 19, 2025
Grant date	—

Abstract

There are provided a memory device and an operating method of the memory device. The memory device includes: a memory block including a plurality of memory cells; a peripheral circuit configured to perform a plurality of read voltage applying operations and a plurality of word line setting operations on the memory block; and control logic configured to control the peripheral circuit to perform a plurality of word line setting operations to set a plurality of word line potentials of word lines included in the memory block, wherein at least one word line setting operation among the plurality of word line setting operations is used to set a word line potential higher than a word line potential set by the other word line setting operations.

First claim

What is claimed is:

1 . A memory device comprising:
a memory block including a plurality of memory cells; a peripheral circuit configured to perform a plurality of read voltage applying operations and a plurality of word line setting operations on the memory block; and control logic configured to control the peripheral circuit to perform a plurality of word line setting operations to set a plurality of word line potentials of word lines included in the memory block, wherein at least one word line setting operation among the plurality of word line setting operations is used to set a word line potential higher than a word line potential set by the other word line setting operations.

2 . The memory device of claim 1 , wherein the plurality of memory cells are capable of being in an erase state and a plurality of program states, and the peripheral circuit applies, to a selected word line among the word lines, at least one read voltage among a plurality of read voltages for distinguishing the erase state and the plurality of program states in each of the plurality of read voltage applying operations.

3 . The memory device of claim 2 , wherein the peripheral circuit:
performs any one of the plurality of word line setting operations between the plurality of read voltage applying operations; and performs the at least one word line setting operation just before a specific read voltage applying operation using at least one highest read voltage among the plurality of read voltage applying operations is performed.

4 . The memory device of claim 2 , wherein each of the plurality of read voltage applying operations corresponds to a least significant bit, a center significant bit, and a most significant bit of the memory cells.

5 . The memory device of claim 1 , wherein the peripheral circuit controls the word lines to have a first voltage level in the at least one word line setting operation, and controls the word lines to have a second voltage level in the other word line setting operations, and
wherein the first voltage level is a positive voltage level higher than zero volts.

6 . The memory device of claim 5 , wherein the peripheral circuit controls the word lines to have the second voltage level before a first read voltage applying operation among the plurality of read voltage applying operations is performed.

7 . The memory device of claim 5 , wherein the peripheral circuit controls the word lines to have the second voltage level after a last read voltage applying operation among the plurality of read voltage applying operations is performed.

8 . The memory device of claim 1 , wherein the control logic includes a word line voltage setting component, and
wherein the word line voltage setting component is configured to set a word line potential in each of the plurality of word line setting operations.

9 . A memory device comprising:
a memory block including a plurality of memory cells; a peripheral circuit configured to alternately perform a plurality of read voltage applying operations and a plurality of word line setting operations on the memory block; and control logic configured to set a first specific word line setting operation among the plurality of word line setting operations, which is performed just before a first specific read voltage applying operation using a highest read voltage among the plurality of read voltage applying operations, to a word line potential higher than a word line potential of the other word line setting operations, and control the peripheral circuit such that word lines of the memory block have the set word line potential.

10 . The memory device of claim 9 , wherein the control logic sets a second specific word line setting operation among the plurality of word line setting operations, which is performed just before a second specific read voltage applying operation using a second highest read voltage among the plurality of read voltage applying operations, to a word line potential which is lower than the word line potential of the first specific word line setting operation and is higher than a word line potential of the other word line setting operations except the first specific word line setting operation and the second specific word line setting operation.

11 . The memory device of claim 10 , wherein the peripheral circuit controls the word lines to have a first voltage level in the first specific word line setting operation, and controls the word lines to have a second voltage level in the other word line setting operations except the first specific word line setting operation and the second specific word line setting operation, and
wherein the first voltage level is a positive voltage level higher than zero volts.

12 . The memory device of claim 11 , wherein the peripheral circuit controls the word lines to have a third voltage level in the second specific word line setting operation, and
wherein the third voltage level is a positive voltage level higher than zero volts.

13 . The memory device of claim 11 , wherein the peripheral circuit controls the word lines to have the second voltage level before a first read voltage applying operation among the plurality of read voltage applying operations is performed.

14 . The memory device of claim 11 , wherein the peripheral circuit controls the word lines to have the second voltage level after a last read voltage applying operation among the plurality of read voltage applying operations is performed.

15 . A method of operating a memory device, the method comprising:
performing a first word line setting operation of controlling a plurality of word lines of a memory block to have a first voltage level; performing a first read voltage applying operation on a selected word line; performing a second word line setting operation of controlling the selected word line to have a second voltage level after the first read voltage applying operation is performed; performing a second read voltage applying operation on the selected word line; performing a third word line setting operation of controlling the selected word line to have a third voltage level after the second read voltage applying operation is performed; and performing a third read voltage applying operation on the selected word line, wherein the third voltage level of the third word line setting operation performed just before the third read voltage applying operation using a highest read voltage among the first read voltage applying operation, the second read voltage applying operation, and the third read voltage applying operation is performed is higher than each of the first voltage level and the second voltage level.

16 . The method of claim 15 , wherein the third voltage level is higher than zero volts.

17 . The method of claim 15 , wherein the second voltage level of the second word line setting operation performed just before the second read voltage applying operation using a second highest read voltage among the first read voltage applying operation, the second read voltage applying operation, and the third read voltage applying operation is performed is higher than the first voltage level and is lower than the third voltage level.

18 . The method of claim 17 , wherein the second voltage level is higher than zero volts.

19 . The method of claim 15 , wherein the first read voltage applying operation is an operation for reading a least significant bit of memory cells connected to the selected word line,
wherein the second read voltage applying operation is

Assignees

• Sk Hynix Inc

Inventors

• Lee Hee Youl

Classifications

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/34

  Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/24

  Bit-line control circuits · CPC title

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title