Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2025194124-A1
Application number	US-202418756902-A
Country	US
Kind code	A1
Filing date	Jun 27, 2024
Priority date	Dec 11, 2023
Publication date	Jun 12, 2025
Grant date	—

Abstract

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate and an epi layer on an upper surface of the substrate. The semiconductor device also includes a P region located within the epi layer, at least one N+ region located within the P region, and at least one insulating layer in contact with the epi layer, the epi layer, the P region, and the at least one N+ region. The semiconductor device further includes an anode on the P region, the N+ region, and the insulating layer.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a substrate; an epi layer on an upper surface of the substrate; a P region located within the epi layer; at least one N+ region located within the P region; at least one insulating layer in contact with the epi layer, the P region, and the at least one N+ region; and an anode provided on the P region, the at least one N+ region, and the at least one insulating layer.

2 . The semiconductor device of claim 1 , wherein the at least one insulating layer is one of:
located on upper surfaces of the epi layer, the P region, and the at least one N+ region; or located in a trench structure along sides of the P region and the at least one N+ region within the epi layer.

3 . The semiconductor device of claim 1 , wherein the substrate includes at least one of an N+ type substrate, a P+ type substrate, or any combination thereof.

4 . The semiconductor device of claim 1 , wherein the epi layer includes at least one of an N− type epi layer, a P− type epi layer, or any combination thereof.

5 . The semiconductor device of claim 1 , wherein the semiconductor device further includes a P-well region or an N-well region located between the epi layer and the P region within the epi layer.

6 . The semiconductor device of claim 5 , wherein the P region includes a P+ type.

7 . The semiconductor device of claim 1 , wherein the semiconductor device further includes:
a P-well region located between the epi layer and the P region within the epi layer; and an N region located between the P-well region and the P region.

8 . The semiconductor device of claim 7 , wherein the P region includes a P+ type.

9 . The semiconductor device of claim 1 , wherein:
the at least one N+ region includes a number of N+ regions in the range of two to four N+ regions; and the at least one insulating layer includes a number of insulating layers in the range of two to four insulating layers.

10 . The semiconductor device of claim 1 , wherein the semiconductor device further includes a cathode, and wherein the cathode is located on a lower surface of the substrate or is spaced apart in a same layer as the anode.

11 . The semiconductor device of claim 1 , wherein, in an on state, an inversion channel is formed in a portion where the P region and the at least one insulating layer contact each other.

12 . A method of manufacturing a semiconductor device, the method comprising:
forming an epi layer on an upper surface of a substrate; forming a P region in the epi layer through ion implantation; forming at least one N+ region within the P region through ion implantation; forming at least one insulating layer at a location in contact with the epi layer, the P region, and the at least one N+ region; and forming an anode on the P region, the at least one N+ region, and the at least one insulating layer.

13 . The method of claim 12 , wherein forming the P region includes patterning by placing a mask on the epi layer before the ion implantation.

14 . The method of claim 12 , wherein forming the at least one N+ region includes patterning by placing a mask on the P region and the epi layer before the ion implantation.

15 . The method of claim 12 , wherein forming the at least one insulating layer includes one of:
forming the at least one insulating layer on upper surfaces of the epi layer, the P region, and the at least one N+ region; or forming the at least one insulating layer in a trench structure along sides of the P region and the at least one N+ region within the epi layer.

16 . The method of claim 12 , further comprising, after forming the epi layer and before forming the P region, forming a P-well region or an N-well region within the epi layer between the epi layer and the P region.

17 . The method of claim 12 , further comprising, after forming the epi layer and before forming the P region:
forming a P-well region within the epi layer between the epi layer and the P region; and forming an N region between the P-well region and the P region.

18 . The method of claim 12 , wherein:
forming the at least one N+ region includes forming a number of N+ regions in the range of two to four N+ regions through ion implantation in the P region, and forming the at least one insulating layer includes forming a number of insulating layers in the range of two to four insulating layers on upper surfaces of the epi layer, the P region, and the N+ region.

19 . The method of claim 12 , wherein further comprising, after forming the anode, forming a cathode on a lower surface of the substrate or spaced apart in a same layer as the anode.

Assignees

• Hyundai Motor Co Ltd
• Kia Corp

Inventors

• Joo Nackyong
• Chun Dae Hwan
• Hong Jungyeop
• Kim Taehyun
• Jung Youngkyun
• Park Junghee

Classifications

• H10D62/8325

  Silicon carbide · CPC title

• H10D8/045

  of PN junction diodes · CPC title

• H10D8/051

  of Schottky diodes · CPC title

• H10D8/00 Primary

  Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00) · CPC title

• H10D64/117

  Recessed field plates, e.g. trench field plates or buried field plates · CPC title