Mesh decoding device, mesh decoding method, and program

Patent metadata

Field	Value
Publication number	US-2025193454-A1
Application number	US-202519061106-A
Country	US
Kind code	A1
Filing date	Feb 24, 2025
Priority date	Dec 28, 2022
Publication date	Jun 12, 2025
Grant date	—

Abstract

A displacement decoding unit 206 of a mesh decoding device 200 according to the present invention includes a circuit, wherein the circuit: generates a binarization syntax by performing arithmetic decoding on a displacement bit stream, generates a binarization syntax by performing bypass arithmetic decoding that performs arithmetic decoding while fixing a context value on the displacement bit stream, generates a syntax by multi-value conversion of the binarization syntax, and generates a coefficient level value from the syntax.

First claim

1 . A mesh decoding device comprising:
a circuit that decodes a displacement bit stream to generate and output a displacement, wherein the circuit:
generates a binarization syntax by performing arithmetic decoding on the displacement bit stream;
generates a binarization syntax by performing bypass arithmetic decoding in which arithmetic decoding is performed while a context value is fixed with respect to the displacement bit stream;
generates the syntax by multi-value conversion of the binarization syntax;
generates a coefficient level value from the syntax x;
generates a transformed coefficient by inversely quantizing the coefficient level value; and
generates a displacement by applying an inverse wavelet transform to the transformed coefficient.

2 . The mesh decoding device according to claim 1 , wherein
the circuit:
decodes the binarization syntax in units of sub-blocks,
decodes the binarization syntax in units of sub-blocks,
generates the syntax in units of sub-blocks, and
generates the coefficient level value in units of sub-blocks.

3 . The mesh decoding device according to claim 2 , wherein
the circuit determines whether decoding of some syntax is omitted and the syntax is regarded as a predetermined value, and in a case where a total number of decoded values in each sub-block reaches a predetermined threshold or in a case where a total number of the decoded values of 1 in each sub-block reaches the predetermined threshold, the circuit performs the bypass arithmetic decoding on all remaining flags indicating whether the remaining flags are non-zero coefficients.

4 . The mesh decoding device according to claim 2 , wherein
in a case where a total number of decoded values in each sub-block reaches a predetermined threshold or in a case where a total number of the decoded values of 1 in each sub-block reaches the predetermined threshold, the circuit performs the bypass arithmetic decoding on all remaining flags indicating whether an absolute value of a coefficient is 2 or more.

5 . A mesh decoding method comprising:
decoding a displacement bit stream to generate and output a displacement, wherein the decoding includes: generating a binarization syntax by performing arithmetic decoding on the displacement bit stream; generating a binarization syntax by performing bypass arithmetic decoding in which arithmetic decoding is performed while a context value is fixed with respect to the displacement bit stream; generating the syntax by multi-value conversion of the binarization syntax; generating a coefficient level value from the syntax; generating a transformed coefficient by inversely quantizing the coefficient level value; and generating a displacement by applying an inverse wavelet transform to the transformed coefficient.

6 . A program stored on a non-transitory computer-readable medium for causing a computer to function as a mesh decoding device, wherein
the mesh decoding device includes a circuit, and the circuit:
decodes a displacement bit stream to generate and output a displacement, and
the displacement decoding unit includes:
generates a binarization syntax by performing arithmetic decoding on the displacement bit stream;
generates a binarization syntax by performing bypass arithmetic decoding in which arithmetic decoding is performed while a context value is fixed with respect to the displacement bit stream;
generates the syntax by multi-value conversion of the binarization syntax;
generates a coefficient level value from the syntax;
generates a transformed coefficient by inversely quantizing the coefficient level value; and
generates a displacement by applying an inverse wavelet transform to the transformed coefficient.

Assignees

• Kddi Corp

Inventors

• Nishimura Hitoshi
• Kawamura Kei

Classifications

• H04N19/63

  using sub-band based transform, e.g. wavelets · CPC title

• H04N19/13

  Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC] · CPC title

• H04N19/176

  the region being a block, e.g. a macroblock · CPC title

• H04N19/70 Primary

  characterised by syntax aspects related to video coding, e.g. related to compression standards · CPC title

• H04N19/91

  Entropy coding, e.g. variable length coding [VLC] or arithmetic coding · CPC title