Decoder circuit and display device

Patent metadata

Field	Value
Publication number	US-2025191531-A1
Application number	US-202318832951-A
Country	US
Kind code	A1
Filing date	Sep 26, 2023
Priority date	Nov 21, 2022
Publication date	Jun 12, 2025
Grant date	—

Abstract

A decoder circuit and a display device are provided, which belong to the technical field of electronics. In each logic circuit group included in the decoder circuit, N-type transistors and P-type transistors are both arranged along a second direction, the N-type transistors and the P-type transistors are arranged along a first direction intersected with the second direction, substrate isolation regions of any transistor are disposed on two sides of the transistor in the first direction, and the substrate isolation region is provided with vias arranged along the second direction. In this way, the P-type transistor and the N-type transistor can be separated by the substrate isolation region with vias, so that a distance between the P-type transistor and the N-type transistor adjacent to each other is greater than a distance between two adjacent transistors of the same type (e.g., N-type transistors or P-type transistors).

First claim

1 . A decoder circuit, comprising:
a plurality of logic circuit groups arranged sequentially along a first direction and connected in series; each of the logic circuit groups comprising: a plurality of logic circuits arranged sequentially along a second direction and connected in series, the second direction being intersected with the first direction; each of the logic circuits comprising: at least one N-type transistor and at least one P-type transistor, wherein each of the at least one N-type transistor and the at least one P-type transistor has a channel region and two substrate isolation regions, the two substrate isolation regions being respectively disposed on two sides of the channel region in the first direction, and each of the substrate isolation regions is provided with a plurality of vias arranged sequentially along the second direction; wherein in each of the logic circuit groups, N-type transistors in the plurality of logic circuits are arranged sequentially along the second direction, P-type transistors in the plurality of logic circuits are arranged sequentially along the second direction, a set of the P-type transistors and a set of the N-type transistors are arranged sequentially along the first direction, and a distance between a channel region of a P-type transistor and a channel region of a N-type transistor adjacent to the P-type transistor in the first direction is greater than a distance between channel regions of two adjacent transistors in each of the set of the P-type transistors and the set of the N-type transistors.

2 . The decoder circuit according to claim 1 , wherein each two adjacent logic circuit groups are arranged in mirror symmetry along an axis extending in the second direction.

3 . The decoder circuit according to claim 2 , wherein in each two adjacent logic circuit groups, transistors disposed on two sides of the axis share one substrate isolation region which is between the two adjacent logic circuit groups.

4 . The decoder circuit according to claim 1 , wherein in two adjacent substrate isolation regions respectively in a P-type transistor and a N-type transistor which are adjacent in the first direction, a distance between an edge of one substrate isolation region away from the other substrate isolation region and an edge of the other substrate isolation region away from the one substrate isolation region is greater than the distance between the channel regions of two adjacent transistors in each of the set of the P-type transistors and the set of the N-type transistors.

5 . The decoder circuit according to claim 1 , wherein for each transistor in a P-type transistor and a N-type transistor which are adjacent in the first direction, a distance between a substrate isolation region in the transistor and close to another transistor adjacent to the transistor and a channel region of the transistor is greater than a distance between a substrate isolation region in the transistor and away from the another transistor adjacent to the transistor and the channel region of the transistor.

6 . The decoder circuit according to claim 1 , wherein the distance between a channel region of a P-type transistor and a channel region of a N-type transistor adjacent to the P-type transistor in the first direction is greater than a difference between a width of the channel region of the P-type transistor and a width of the channel region of the N-type transistor, the width of the channel region of the P-type transistor is greater than the width of the channel region of the N-type transistor, and a direction of both the widths is parallel to the first direction.

7 . The decoder circuit according to claim 1 , wherein an area of the substrate isolation region of the P-type transistor is greater than an area of the substrate isolation region of the N-type transistor.

8 . The decoder circuit according to claim 1 , wherein in each of the logic circuits, substrate isolation regions of P-type transistors disposed on the same side of channel regions of the P-type transistors are connected and flush in the second direction, and the channel regions of the P-type transistors are spaced apart from each other and edges of at least one side of the channel regions are flush in the second direction;
and substrate isolation regions of N-type transistors disposed on the same side of channel regions of the N-type transistors are connected and flush in the second direction, and the channel regions of the N-type transistors are spaced apart from each other and edges of at least one side of the channel regions are flush in the second direction.

9 . The decoder circuit according to claim 1 , wherein each of the at least one N-type transistor and the at least one P-type transistor has a gate layer and a source-drain metal layer which are rectangular in a top view;
and the gate layer and the source-drain metal layer overlap with each other, a length direction of the gate layer extends along the first direction, and a length direction of the source-drain metal layer extends along the second direction; wherein the channel region overlaps with an overlapping region of the gate layer and the source-drain metal layer.

10 . The decoder circuit according to claim 1 , wherein each of the logic circuits is further respectively connected to a first DC power supply line and a second DC power supply line and is configured to perform logic processing based on a signal provided by the first DC power supply line and a signal provided by the second DC power supply line.

11 . The decoder circuit according to claim 10 , wherein the first DC power supply line and the second DC power supply line are respectively disposed on two sides of the plurality of logic circuit groups in the second direction and both extend along the first direction, and the width of the first DC power supply line in the second direction is equal to the width of the second DC power supply line in the second direction.

12 . The decoder circuit according to claim 1 , wherein the decoder circuit is disposed on one side of a substrate, at least a part of connections in the decoder circuit is realized by a plurality of layers of metal wires stacked sequentially in a direction away from the substrate, each two adjacent layers of metal wires are connected with each other through a via hole.

13 . The decoder circuit according to claim 12 , wherein at least a part of connections in the decoder circuit is realized by a total of three layers of metal wires comprising a first metal wire, a second metal wire and a third metal wire which are sequentially stacked in the direction away from the substrate;
wherein the first metal wire comprises a plurality of line segments extending along the first direction and a plurality of line segments extending along the second direction, the second metal wire comprises a plurality of line segments extending along the second direction, and the third metal wire comprises a plurality of line segments extending along the first direction; and both the first DC power supply line and the second DC power supply line connected to each of the logic circuits are disposed in the same layer as the third metal wire.

14 . The decoder circuit according to claim 1 , wherein the decoder circuit is a 3-to-8 decoder circuit; and the plurality of logic circuit groups are classified into a first logic circuit group and eight second logic circuit groups arranged sequentially along the first direction;
a plurality of logic circuits in the first logic circuit group comprises: three first NOT gates and a two-input NAND gate arranged sequentially along the second direction; and a plurali

Assignees

• Yunnan Invensight Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Jiang Shanghong
• Shan Qingshan
• Fan Longfei
• Li Dachao
• Lu Pengcheng
• Ma Yaoxi

Classifications

• H10D89/10

  Integrated device layouts · CPC title

• H10D84/854

  comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for latchup prevention · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G3/3225 Primary

  using an active matrix · CPC title

• H10D86/471

  having different architectures, e.g. having both top-gate and bottom-gate TFTs · CPC title