Gate driving circuit, display device including the gate driving circuit and electronic device including the display device

Patent metadata

Field	Value
Publication number	US-2025186051-A1
Application number	US-202519017802-A
Country	US
Kind code	A1
Filing date	Jan 13, 2025
Priority date	Apr 25, 2008
Publication date	Jun 12, 2025
Grant date	—

Abstract

A gate driving circuit includes a normal output circuit configured to output a first gate signal at a first output node and a second gate signal at a second output node in response to a previous first gate signal and a first clock signal. The first gate signal and the second gate signal are opposite in phase to each other, and the first gate signal and the second gate signal are applied to different transistors included in a pixel circuit.

First claim

What is claimed is:

1 . A gate driving circuit comprising:
a normal output circuit configured to output a first gate signal at a first output node and a second gate signal at a second output node in response to a previous first gate signal and a first clock signal, wherein a phase of the first gate signal is opposite to a phase of the second gate signal, and wherein the first gate signal and the second gate signal are applied to different transistors included in a pixel circuit.

2 . The gate driving circuit of claim 1 , wherein the normal output circuit includes:
a ninth transistor including a control electrode configured to receive the first clock signal, a first electrode configured to receive the previous first gate signal and a second electrode connected to a first node; a tenth transistor including a control electrode connected to the first node, a first electrode configured to receive a first gate power supply voltage and a second electrode connected to the second output node; an eleventh transistor including a first electrode connected to the second output node and a second electrode configured to receive a second gate power supply voltage; a twelfth transistor including a control electrode configured to receive the second gate power supply voltage, a first electrode connected to the first node and a second electrode connected to a second node; a thirteenth transistor including a control electrode connected to the second output node, a first electrode configured to receive the first gate power supply voltage and a second electrode connected to the first output node; a fourteenth transistor including a control electrode connected to the second node, a first electrode connected to the first output node and a second electrode configured to receive the second gate power supply voltage; a first capacitor including a first electrode connected to the second node and a second electrode connected to the first output node; and a second capacitor including a first electrode configured to receive the first gate power supply voltage and a second electrode connected to the second output node.

3 . The gate driving circuit of claim 2 , wherein the eleventh transistor further includes a control electrode connected to the second node.

4 . The gate driving circuit of claim 2 , wherein the eleventh transistor further includes a control electrode connected to the first node.

5 . The gate driving circuit of claim 2 , wherein the normal output circuit further includes a reset transistor including a control electrode configured to receive a reset signal, a first electrode connected to the second output node and a second electrode configured to receive the second gate power supply voltage.

6 . A gate driving circuit comprising:
a normal output circuit configured to output a first gate signal at a first output node and control a voltage of a second output node in response to a previous first gate signal and a first clock signal; and an inverted output circuit configured to output a third gate signal at a third output node in response to a second clock signal and the voltage of the second output node, wherein a phase of the first gate signal is opposite to a phase of the third gate signal, and wherein the first gate signal and the third gate signal are applied to different transistors included in a pixel circuit.

7 . The gate driving circuit of claim 6 , wherein the inverted output circuit includes:
a fifteenth transistor including a control electrode configured to receive the second clock signal, a first electrode connected to the second output node and a second electrode connected to a buffer node; a sixteenth transistor including a control electrode configured to receive a second gate power supply voltage, a first electrode connected to the buffer node and a second electrode connected to a third node; a seventeenth transistor including a control electrode connected to the third node, a first electrode configured to receive the second gate power supply voltage and a second electrode connected to the third output node; an eighteenth transistor including a first electrode connected to the third output node and a second electrode configured to receive a first gate power supply voltage; and a third capacitor including a first electrode connected to the third node and a second electrode connected to the third output node.

8 . The gate driving circuit of claim 7 , wherein the normal output circuit includes:
a ninth transistor including a control electrode configured to receive the first clock signal, a first electrode configured to receive the previous first gate signal and a second electrode connected to a first node; a tenth transistor including a control electrode connected to the first node, a first electrode configured to receive the first gate power supply voltage and a second electrode connected to the second output node; an eleventh transistor including a first electrode connected to the second output node and a second electrode configured to receive the second gate power supply voltage; a twelfth transistor including a control electrode configured to receive the second gate power supply voltage, a first electrode connected to the first node and a second electrode connected to a second node; a thirteenth transistor including a control electrode connected to the second output node, a first electrode configured to receive the first gate power supply voltage and a second electrode connected to the first output node; a fourteenth transistor including a control electrode connected to the second node, a first electrode connected to the first output node and a second electrode configured to receive the second gate power supply voltage; a first capacitor including a first electrode connected to the second node and a second electrode connected to the first output node; and a second capacitor including a first electrode configured to receive the first gate power supply voltage and a second electrode connected to the second output node.

9 . The gate driving circuit of claim 8 , wherein the eighteenth transistor further includes a control electrode connected to the first output node.

10 . The gate driving circuit of claim 8 , wherein the eighteenth transistor further includes a control electrode connected to the second node.

11 . The gate driving circuit of claim 8 , wherein the normal output circuit further includes a reset transistor including a control electrode configured to receive a reset signal, a first electrode connected to the second output node and a second electrode configured to receive the second gate power supply voltage.

12 . A display device comprising:
a display panel including a pixel circuit; a gate driving circuit configured to output a gate signal to the pixel circuit; a data driving circuit configured to output a data voltage to the pixel circuit; and an emission driving circuit configured to output an emission signal to the pixel circuit, wherein the pixel circuit includes: a light emitting element; a first transistor configured to apply a driving current to the light emitting element; a second transistor including a first electrode configured to receive a bias voltage and a second electrode connected to a first electrode of the first transistor; and a third transistor including a first electrode connected to an anode electrode of the light emitting element and a second electrode configured to receive a first initialization voltage; and wherein one of the second transistor and the third transistor is a P-type transistor and an other one of the second transistor and the third transistor is an N-type transistor.

Assignees

• Samsung Display Co Ltd

Inventors

• Lee Wonjun
• Son Sungmin
• Kim Minji
• Moon Geumju

Classifications

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G3/30

  using electroluminescent panels · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G2310/02

  Addressing, scanning or driving the display screen or processing steps related thereto · CPC title

• G09G2300/0809

  Several active elements per pixel in active matrix panels · CPC title