Semiconductor package

Patent metadata

Field	Value
Publication number	US-2025183107-A1
Application number	US-202418954917-A
Country	US
Kind code	A1
Filing date	Nov 21, 2024
Priority date	Dec 1, 2023
Publication date	Jun 5, 2025
Grant date	—

Abstract

A semiconductor package including a package substrate including a first conductive pad, a semiconductor chip disposed on the package substrate and including a second conductive pad, a first adhesive layer formed between the package substrate and the semiconductor chip, a second adhesive layer formed along a side wall of the semiconductor chip, and a conductive line electrically connecting the second conductive pad to the first conductive pad of the package substrate. The first adhesive layer and the second adhesive layer are formed from the same adhesive material and are formed continuously without a boundary therebetween and an outer surface of the second adhesive layer has a slope extending downwardly and outwardly toward the upper surface of the package substrate from the side wall of the semiconductor chip.

First claim

What is claimed is:

1 . A semiconductor package comprising:
a package substrate comprising one or more first conductive pads on an upper surface thereof; a semiconductor chip disposed on the package substrate and comprising one or more second conductive pads on an upper surface thereof; a first adhesive layer, having electrical insulation characteristics, formed between the package substrate and the semiconductor chip; a second adhesive layer, having electrical insulation characteristics, formed along a first side wall of the semiconductor chip; and a conductive line electrically connecting the second conductive pad of the semiconductor chip to the first conductive pad of the package substrate, wherein the first adhesive layer and the second adhesive layer include the same adhesive material and are formed continuously without a boundary therebetween by pressing the same adhesive material between the package substrate and the semiconductor chip, and an outer surface of the second adhesive layer has a first slope extending downwardly and outwardly toward the upper surface of the package substrate from the first side wall.

2 . The semiconductor package of claim 1 , wherein the second adhesive layer contacts the first side wall of the semiconductor chip so that the conductive line is electrically insulated from the first side wall of the semiconductor chip.

3 . The semiconductor package of claim 1 , wherein
the semiconductor chip includes a second side wall opposing the first side wall, the second adhesive layer being formed along the second side wall, an outer surface of the second adhesive layer formed along the second side wall has a second slope extending downwardly and outwardly toward the upper surface of the package substrate from the second side wall, and the first slope and the second slope are the same.

4 . The semiconductor package of claim 1 , wherein an inclination angle of the first slope of the second adhesive layer does not exceed about 45 degrees.

5 . A semiconductor package comprising:
a package substrate comprising one or more first conductive pads on an upper surface thereof; a plurality of semiconductor chips stacked on the package substrate, each semiconductor chip comprising one or more second conductive pads on each upper surface thereof, wherein respective first side walls of the plurality of semiconductor chips are stacked on each other to have a step shape; a plurality of first adhesive layers, having electrical insulation characteristics, formed between the plurality of semiconductor chips and between the package substrate and the semiconductor chip arranged at a lowermost position among the plurality of semiconductor chips, the plurality of first adhesive layers insulating the plurality of semiconductor chips from each other; a plurality of second adhesive layers, having electrical insulation characteristics, formed to correspond to each of the plurality of first adhesive layers along each first side wall of the plurality of semiconductor chips; and a conductive line electrically connecting the second conductive pads of the semiconductor chips to the first conductive pad of the package substrate, wherein the first adhesive layers and the second adhesive layers formed to correspond to each other are formed from the same adhesive material, and are formed continuously without a boundary therebetween by pressing the same adhesive material between the plurality of semiconductor chips and between the package substrate and the semiconductor chip arranged at the lowermost position among the plurality of semiconductor chips, and outer surfaces of the second adhesive layers have a slope extending downwardly and outwardly toward the upper surface of the package substrate from the first side walls of the semiconductor chips.

6 . The semiconductor package of claim 5 , wherein
the second adhesive layers contact the first side walls of the semiconductor chips so that the conductive line is electrically insulated from the first side walls of the semiconductor chips.

7 . The semiconductor package of claim 5 , further comprising electrical insulating layers disposed between the conductive line and the first side walls of the plurality of semiconductor chips.

8 . The semiconductor package of claim 5 , wherein the slope of the second adhesive layers has a convex shape.

9 . The semiconductor package of claim 5 , wherein an inclination angle of the slope of the second adhesive layers does not exceed about 45 degrees.

10 . The semiconductor package of claim 5 , wherein each of the second adhesive layers correspondingly contact at least a portion of the first side wall of each of the semiconductor chips.

11 . The semiconductor package of claim 5 , wherein each of the second adhesive layers correspondingly contacts at least a portion of the upper surface of each of the semiconductor chips beyond the first side wall thereof.

12 . The semiconductor package of claim 5 , wherein
the plurality of semiconductor chips have the same size as each other, the plurality of semiconductor chips each include a second side wall opposing a corresponding first side wall, a third side wall, and a fourth side wall opposing a corresponding second side wall, and the plurality of semiconductor chips are aligned so that a plurality of third side walls of the plurality of semiconductor chips coincide with each other in a vertical direction and a plurality of fourth side walls thereof coincide with each other in the vertical direction, each of the first side walls is between each of the third side walls and each of the fourth side walls, and the conductive line is formed along the first side walls.

13 . The semiconductor package of claim 12 , wherein
a thickness of the first adhesive layer between the semiconductor chip arranged at the lowermost position among the semiconductor chips and the package substrate is greater than a thickness of the first adhesive layer between the plurality of semiconductor chips.

14 . The semiconductor package of claim 12 , wherein a thickness of the first adhesive layer between the plurality of semiconductor chips increases or decreases away from the package substrate.

15 . The semiconductor package of claim 12 , wherein
the plurality of semiconductor chips each include a second side wall opposing a corresponding first side wall, the respective second side walls of the plurality of semiconductor chips are stacked on each other to have a reverse-step shape, and the second adhesive layers are integrally formed along the second side walls of the plurality of semiconductor chips and are in contact with each other.

16 . The semiconductor package of claim 5 , wherein
the plurality of semiconductor chips have different surface areas, and the size of the surface areas of the semiconductor chips decrease in a direction extending away from the package substrate.

17 . The semiconductor package of claim 16 , wherein
the plurality of semiconductor chips each include a second side wall opposing a corresponding first side wall, the second adhesive layer being formed along the second side wall of the respective semiconductor chips, and the second adhesive layer formed along the first side wall of the respective semiconductor chips being symmetrical to the second adhesive layer formed along the second side wall of the respective semiconductor chips.

18 . A semiconductor package comprising:
a package substrate comprising one or more first conductive pads on an upper surface thereof; a pluralit

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Kwangyong

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W74/117 Primary

  the substrate having spherical bumps for external connection · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title