Semiconductor device

Patent metadata

Field	Value
Publication number	US-2025176163-A1
Application number	US-202418827242-A
Country	US
Kind code	A1
Filing date	Sep 6, 2024
Priority date	Nov 24, 2023
Publication date	May 29, 2025
Grant date	—

Abstract

A semiconductor device includes a channel pattern on a substrate and extending in a first direction perpendicular to a surface of the substrate, a gate insulation layer on a sidewall of the channel pattern, the gate insulation layer having an upper surface higher than an uppermost surface of the channel pattern, a first gate electrode on the gate insulation layer and having a first work function, a second gate electrode covering a surface of the first gate electrode, the second gate electrode having a second work function that is greater than the first work function, and a first contact plug on the uppermost surface of the channel pattern, the first contact plug contacting an upper portion of the gate insulation layer, where a lower portion of the first contact plug faces at least a portion of the second gate electrode in a second direction intersecting the first direction.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a channel pattern on a substrate, the channel pattern comprising channel pattern sidewall portions extending in a first direction that is perpendicular to a surface of the substrate and a channel pattern lower portion connecting lower ends of the channel pattern sidewall portions that face each other in a second direction intersecting the first direction; a gate insulation layer on surfaces of the channel pattern sidewall portions and the channel pattern lower portion, the gate insulation layer comprising gate insulation layer sidewall portions extending in the first direction and a gate insulation layer lower portion connecting lower ends of the gate insulation layer sidewall portions that face each other in the second direction, the gate insulation layer having an upper surface that is higher than an uppermost surface of the channel pattern; a first gate electrode on an inner surface of at least one of the gate insulation layer sidewall portions, the first gate electrode having a first work function; a second gate electrode covering a surface of the first gate electrode, and the second gate electrode having a second work function that is greater than the first work function; and a first contact plug on the uppermost surface of the channel pattern, the first contact plug contacting an upper portion of the gate insulation layer, wherein an uppermost surface of the second gate electrode is higher than the uppermost surface of the channel pattern.

2 . The semiconductor device of claim 1 , wherein the channel pattern comprises an oxide semiconductor.

3 . The semiconductor device of claim 1 , wherein a height difference between an uppermost surface of the first gate electrode and the uppermost surface of the channel pattern is less than a height difference between the uppermost surface of the second gate electrode and the uppermost surface of the channel pattern.

4 . The semiconductor device of claim 3 , wherein the uppermost surface of the first gate electrode is coplanar with the uppermost surface of the channel pattern.

5 . The semiconductor device of claim 1 , wherein a height difference between an uppermost surface of the first gate electrode and the uppermost surface of the channel pattern is less than 5% of a vertical height of the channel pattern.

6 . The semiconductor device of claim 1 , wherein the first contact plug has a third work function that is equal to or less than the first work function.

7 . The semiconductor device of claim 1 , wherein the first contact plug comprises an upper portion having a first width and a lower portion having a second width that is less than the first width.

8 . The semiconductor device of claim 7 , wherein the lower portion of the first contact plug faces the gate insulation layer and the second gate electrode in the second direction.

9 . The semiconductor device of claim 1 , wherein the gate insulation layer comprises metal oxide having a dielectric constant that is greater than a dielectric constant of silicon nitride, and
wherein the first gate electrode comprises a metal.

10 . The semiconductor device of claim 1 , wherein the first gate electrode comprises titanium or titanium nitride, and
wherein the second gate electrode comprises Ni or Ru.

11 . The semiconductor device of claim 1 , further comprising a capacitor on the first contact plug,
wherein the capacitor is connected to the first contact plug.

12 . The semiconductor device of claim 1 , further comprising a mold insulation structure on an outer surface of the channel pattern,
wherein the mold insulation structure has an upper surface that is higher than the uppermost surface of the channel pattern.

13 . A semiconductor device, comprising:
a first conductive layer pattern on a substrate, the first conductive layer pattern extending in a first direction that is parallel to an upper surface of the substrate; a channel pattern on the first conductive layer pattern, the channel pattern comprising channel pattern sidewall portions extending in a second direction intersecting the first direction and a channel pattern lower portion connecting lower ends of the channel pattern sidewall portions that face each other in the first direction, wherein a lower surface of the channel pattern contacts the first conductive layer pattern; a gate insulation layer on surfaces of the channel pattern sidewall portions and the channel pattern lower portion, the gate insulation layer comprising gate insulation layer sidewall portions extending in the second direction and a gate insulation layer lower portion connecting lower ends of the gate insulation layer sidewall portions that face each other in the first direction, the gate insulation layer having an upper surface that is higher than an uppermost surface of the channel pattern; a first gate electrode disposed on an inner surface of at least one of the gate insulation layer sidewall portions, the first gate electrode extending in the third direction intersecting the first direction and parallel to the upper surface of the substrate, the first gate electrode having a first work function; a second gate electrode covering a surface of the first gate electrode, the second gate electrode extending in the third direction and having a second work function that is greater than the first work function; and a first contact plug on the uppermost surface of the channel pattern, the first contact plug contacting an upper portion of the gate insulation layer, wherein a height difference between an uppermost surface of the first gate electrode and the uppermost surface of the channel pattern is less than a height difference between an uppermost surface of the second gate electrode and the uppermost surface of the channel pattern.

14 . The semiconductor device of claim 13 , wherein the uppermost surface the second gate electrode is higher than the uppermost surface of the channel pattern.

15 . The semiconductor device of claim 13 , wherein the uppermost surface of the first gate electrode is coplanar with the upper surface of the channel pattern.

16 . The semiconductor device of claim 13 , wherein the second gate electrode faces the first contact plug in the first direction.

17 . The semiconductor device of claim 13 , wherein the first contact plug has a third work function that is equal to or less than the first work function.

18 . A semiconductor device, comprising:
a channel pattern on a substrate, the channel pattern extending in a first direction perpendicular to a surface of the substrate; a gate insulation layer on a sidewall of the channel pattern, the gate insulation layer having an upper surface higher than an uppermost surface of the channel pattern; a first gate electrode on the gate insulation layer, the first gate electrode having a first work function; a second gate electrode covering a surface of the first gate electrode, the second gate electrode having a second work function that is greater than the first work function; and a first contact plug on the uppermost surface of the channel pattern, the first contact plug contacting an upper portion of the gate insulation layer; wherein a lower portion of the first contact plug faces at least a portion of the second gate electrode in a second direction intersecting the first direction.

19 . The semiconductor device of claim 18 , wherein an uppermost surface of the first gate electrode is coplanar with the uppermost surface of the channel patt

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Sungjoon
• Terai Masayuki

Classifications

• H10B12/50

  Peripheral circuit region structures · CPC title

• H10B12/485

  Bit line contacts · CPC title

• H10B12/31 Primary

  having a storage electrode stacked over the transistor · CPC title

• H10B12/315 Primary

  with the capacitor higher than a bit line · CPC title

• H10B12/05 Primary

  Making the transistor · CPC title