Printed circuit board and manufacturing method thereof

US2025176103A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2025176103-A1
Application numberUS-202418883680-A
CountryUS
Kind codeA1
Filing dateSep 12, 2024
Priority dateNov 29, 2023
Publication dateMay 29, 2025
Grant date

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A printed circuit board includes a first insulating layer; a pad portion located on the first insulating layer; a connection layer located on the pad portion and including a central portion and an extension portion extending from the central portion toward an edge of the pad portion; and a second insulating layer located on a portion of the pad portion and a portion of the connection layer, in which the extension portion of the connection layer may be located within a groove portion formed in the second insulating layer, and an upper surface of the extension portion of the connection layer may be covered with the second insulating layer.

First claim

Opening claim text (preview).

What is claimed is: 1 . A printed circuit board, comprising: a first insulating layer; a pad portion located on the first insulating layer; a connection layer located on the pad portion and including a central portion and an extension portion extending from a bottom of the central portion toward a top surface edge of the pad portion; and a second insulating layer disposed on the first insulating layer and covering an exposed portion of the pad portion and a portion of the connection layer, wherein the extension portion of the connection layer is located within a groove portion which is a space formed between the second insulating layer and the pad portion, and an upper surface of the extension portion of the connection layer is covered with the second insulating layer. 2 . The printed circuit board of claim 1 , wherein the groove portion is located on a lower surface of the second insulating layer and on a top of the pad portion. 3 . The printed circuit board of claim 2 , wherein: a lower surface of the extension portion of the connection layer is in contact with the pad portion. 4 . The printed circuit board of claim 3 , wherein the central portion of the connection layer protrudes above the second insulating layer. 5 . The printed circuit board of claim 2 , wherein the connection layer further includes a convex portion extending downward from the central portion and the extension portion. 6 . The printed circuit board of claim 5 , wherein the pad portion includes a concave portion in an upper surface of the pad portion. 7 . The printed circuit board of claim 6 , wherein the convex portion of the connection layer is located within the concave portion of the pad portion. 8 . The printed circuit board of claim 7 , wherein the convex portion of the connection layer is in contact with the pad portion. 9 . The printed circuit board of claim 8 , wherein the central portion of the connection layer protrudes above the second insulating layer. 10 . The printed circuit board of claim 1 , wherein the central portion of the connection layer protrudes above the second insulating layer. 11 . A manufacturing method of a printed circuit board, comprising: forming a pad portion on a first insulating layer; stacking a photosensitive film on the pad portion and the first insulating layer; forming a hole in the photosensitive film; forming a groove portion extending from a bottom of the hole in the photosensitive film; and depositing a metal layer in the hole and the groove portion to form a connection layer including a central portion located in the hole and an extension portion located in the groove portion. 12 . The manufacturing method of claim 11 , further comprising: removing the photosensitive film; and stacking a second insulating layer on the pad portion, the connection layer, and the first insulating layer. 13 . The manufacturing method of claim 12 , further comprising: removing a portion of the second insulating layer such that the central portion of the connection layer protrudes above the second insulating layer. 14 . The manufacturing method of claim 11 , wherein the groove portion is formed on a lower surface of the photosensitive film. 15 . The manufacturing method of claim 14 , wherein: a lower surface of the extension portion of the connection layer is formed on the pad portion to be in contact with the pad portion. 16 . The manufacturing method of claim 11 , further comprising: removing a portion of an upper surface of the pad portion overlapping the hole of the photosensitive film to form a concave portion in the upper surface of the pad portion. 17 . The manufacturing method of claim 16 , wherein the forming of the connection layer further includes forming a convex portion extending downward from the central portion and the extension portion. 18 . The manufacturing method of claim 17 , wherein the convex portion of the connection layer is formed within the concave portion of the pad portion. 19 . The manufacturing method of claim 18 , wherein: the convex portion of the connection layer is formed on the pad portion to be in contact with the pad portion.

Assignees

Inventors

Classifications

  • Surface contacts, e.g. bumps (H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3465) · CPC title

  • by soldering · CPC title

  • H05K1/116Primary

    Lands, clearance holes or other lay-out details concerning the surrounding of a via · CPC title

  • by filling grooves in the support with conductive material (H05K3/045, H05K3/101, H05K3/1258 and H05K3/465 take precedence) · CPC title

  • Coating over pads, e.g. solder resist partly over pads · CPC title

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Frequently asked questions

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What does patent US2025176103A1 cover?
A printed circuit board includes a first insulating layer; a pad portion located on the first insulating layer; a connection layer located on the pad portion and including a central portion and an extension portion extending from the central portion toward an edge of the pad portion; and a second insulating layer located on a portion of the pad portion and a portion of the connection layer, in …
Who is the assignee on this patent?
Samsung Electro Mech
What technology area does this patent fall under?
Primary CPC classification H05K1/116. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu May 29 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).