Display panel and display module, and electronic device

Patent metadata

Field	Value
Publication number	US-2025169309-A1
Application number	US-202519026292-A
Country	US
Kind code	A1
Filing date	Jan 16, 2025
Priority date	Jul 26, 2022
Publication date	May 22, 2025
Grant date	—

Abstract

Embodiments of this application disclose a display panel and a preparation method thereof, and an electronic device, and relate to the field of display technologies, to improve display brightness uniformity of a display panel. The display panel includes: a backplane, an anode layer and a transfer electrode that are located on the backplane, a light emission function layer and a cathode layer that are located on the anode layer and the transfer electrode and that are sequentially stacked, a cathode suppression layer, and an auxiliary cathode. The backplane includes an auxiliary signal line, configured to reduce a voltage drop of the cathode layer. The transfer electrode and the anode layer are disposed on a same layer, and the transfer electrode is electrically connected to the auxiliary signal line. The light emission function layer and the cathode layer are provided with a first opening.

First claim

What is claimed is:

1 . A display panel, wherein the display panel comprises:
a backplane, comprising an auxiliary signal line; an anode layer and a transfer electrode that are located on the backplane, wherein the transfer electrode and the anode layer are disposed on a same layer, and the transfer electrode is electrically connected to the auxiliary signal line; a light emission function layer and a cathode layer that are located on the anode layer and the transfer electrode and that are sequentially stacked, wherein the light emission function layer and the cathode layer are provided with a first opening; a cathode suppression layer, wherein at least a part of the cathode suppression layer is located on the cathode layer, the cathode suppression layer is provided with a second opening, and the second opening at least partially overlaps the first opening, and exposes a part of a surface of the transfer electrode; and an auxiliary cathode, wherein at least a part of the auxiliary cathode is located in the first opening, the auxiliary cathode is connected to the cathode layer and the transfer electrode, and the auxiliary cathode does not overlap the cathode suppression layer.

2 . The display panel of claim 1 , wherein the cathode suppression layer is located on the cathode layer, and an outer boundary of an orthographic projection of the first opening on the backplane coincides with an inner boundary of an orthographic projection of the second opening on the backplane; and
the auxiliary cathode is located in the first opening, and abuts against a part that is of the cathode layer and that surrounds the first opening.

3 . The display panel of claim 1 , wherein the cathode suppression layer is located on the cathode layer, and an outer boundary of an orthographic projection of the first opening on the backplane is located within an inner boundary range of an orthographic projection of the second opening on the backplane; or
a part of the cathode suppression layer is located on the cathode layer, the other part of the cathode suppression layer covers a part of a side wall of the first opening, and an outer boundary of an orthographic projection of the first opening on the backplane intersects with an inner boundary of an orthographic projection of the second opening on the backplane; and a part of the auxiliary cathode is located in the first opening, and the other part of the auxiliary cathode is lapped on the cathode layer.

4 . The display panel of claim 3 , wherein when the cathode suppression layer is located on the cathode layer, and the outer boundary of the orthographic projection of the first opening on the backplane is located within the inner boundary range of the orthographic projection of the second opening on the backplane,
an area of an orthographic projection of the auxiliary cathode on the backplane is greater than an area of a graphic enclosed by the outer boundary of the orthographic projection of the first opening on the backplane.

5 . The display panel of claim 3 , wherein when the cathode suppression layer is located on the cathode layer, and the outer boundary of the orthographic projection of the first opening on the backplane is located within the inner boundary range of the orthographic projection of the second opening on the backplane,
the part that is of the auxiliary cathode and that is lapped on the cathode layer is in a ring shape; or when the part of the cathode suppression layer is located on the cathode layer, the other part of the cathode suppression layer covers the part of the side wall of the first opening, and the outer boundary of the orthographic projection of the first opening on the backplane intersects with the inner boundary of the orthographic projection of the second opening on the backplane, the part that is of the auxiliary cathode and that is lapped on the cathode layer is in a “C” shape or a “-” shape.

6 . The display panel of claim 1 , wherein thickness of the auxiliary cathode is greater than or equal to thickness of the cathode layer.

7 . The display panel of claim 1 , wherein the anode layer comprises an anode;
the display panel further comprises a pixel definition layer located between the anode layer and the light emission function layer, wherein the pixel definition layer is provided with the first opening and a third opening that exposes a part of a surface of the anode, and the light emission function layer is in contact with the anode through the third opening; and an inner boundary of an orthographic projection of the third opening on the backplane does not overlap an outer boundary of an orthographic projection of the auxiliary cathode on the backplane.

8 . The display panel of claim 7 , wherein the inner boundary of the orthographic projection of the third opening on the backplane coincides with an outer boundary of an orthographic projection of the cathode suppression layer on the backplane, or is located within an outer boundary range of an orthographic projection of the cathode suppression layer on the backplane.

9 . The display panel of claim 1 , wherein there are a plurality of auxiliary signal lines; and
extension directions of the plurality of auxiliary signal lines are the same; or at least one auxiliary signal line extends in a first direction, and at least one auxiliary signal line extends in a second direction, wherein the first direction intersects with the second direction.

10 . The display panel of claim 9 , wherein a plurality of transfer electrodes are evenly distributed, or a plurality of auxiliary cathodes are evenly distributed.

11 . The display panel of claim 9 , wherein in a direction from at least one boundary of the display panel to a center of the display panel, distribution density of the transfer electrodes gradually increases, or distribution density of the auxiliary cathodes gradually increases.

12 . The display panel of claim 9 , wherein the backplane comprises a plurality of subpixels arranged in an array shape; and
both the transfer electrode and the auxiliary cathode are in a block shape, the transfer electrode and the auxiliary cathode are disposed in a one-to-one correspondence, and the auxiliary cathode is disposed around the at least one subpixel; or the transfer electrode is in a strip shape, the auxiliary cathode is in a strip shape, the transfer electrode and the auxiliary cathode are disposed in a one-to-one correspondence, and at least one row or at least one column of subpixels are disposed between two adjacent auxiliary cathodes.

13 . The display panel of claim 1 , wherein the backplane comprises:
a substrate; and a semiconductor layer, at least one gate conducting layer, and at least one source/drain conducting layer that are sequentially stacked on the substrate, wherein the auxiliary signal line is located in a target conducting layer, and the target conducting layer comprises any layer in the at least one gate conducting layer and the at least one source/drain conducting layer.

14 . The display panel of claim 13 , wherein there are a plurality of auxiliary signal lines; and
the gate conducting layer comprises a plurality of gate lines that extend in a first direction and that are sequentially arranged in a second direction, the first direction is perpendicular to the second direction, at least a part of auxiliary signal lines extend in the first direction and are sequentially arranged in the second direction, and at least one gate line is disposed between any two adjacent auxiliary signal lines; and/or the source/drain conducting layer comprises a plurality of data lines that exten

Assignees

• Huawei Tech Co Ltd

Inventors

• Liu Guohe
• Zhang Junyong
• Chen Zesheng
• He Hu

Classifications

• H10K59/1201

  Manufacture or treatment · CPC title

• H10K59/873

  Encapsulations · CPC title

• H10K59/1315

  comprising structures specially adapted for lowering the resistance · CPC title

• H10K59/80522 Primary

  combined with auxiliary electrodes · CPC title

• H10D86/443

  adapted for preventing breakage, peeling or short circuiting · CPC title