Logic circuit and semiconductor device

Patent metadata

Field	Value
Publication number	US-2025169184-A1
Application number	US-202519029162-A
Country	US
Kind code	A1
Filing date	Jan 17, 2025
Priority date	Oct 16, 2009
Publication date	May 22, 2025
Grant date	—

Abstract

To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10 −13 A or less per micrometer in channel width. A first signal, a second signal, and a third signal that is a clock signal are input as input signals. A fourth signal and a fifth signal whose voltage states are set in accordance with the first to third signals which have been input are output as output signals.

First claim

1 . A logic circuit comprising:
a transistor comprising an oxide semiconductor layer including a channel formation layer, wherein an off current is 1×10 −13 A or less per micrometer in channel width in the transistor, wherein a first signal, a second signal, and a third signal that is a clock signal are input as input signals, and wherein a fourth signal and a fifth signal whose voltage states are set in accordance with the first signal, the second signal, and the third signal which are input are output as output signals.

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Koyama Jun
• Tsubuku Masashi
• Noda Kosei

Classifications

• G11C19/184

  with field-effect transistors, e.g. MOS-FET · CPC title

• G09G3/36

  using liquid crystals · CPC title

• H03K17/161

  in field-effect transistor switches · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title