Semiconductor device

Patent metadata

Field	Value
Publication number	US-2025169048-A1
Application number	US-202418671559-A
Country	US
Kind code	A1
Filing date	May 22, 2024
Priority date	Nov 21, 2023
Publication date	May 22, 2025
Grant date	—

Abstract

A semiconductor device may include a first lower active contact, a first source/drain pattern on the first lower active contact, a second lower active contact, a second source/drain pattern on the second lower active contact, a lower conductive layer electrically connected to the first and second lower active contacts, a third source/drain pattern and a fourth source/drain pattern between the first and second source/drain patterns, a first upper active contact on the third source/drain pattern, a second upper active contact on the fourth source/drain pattern, and an upper conductive line electrically connected to the first and second upper active contacts. The first to fourth source/drain patterns, the first and second lower active contacts, and the first and second upper active contacts may be disposed between the lower conductive layer and upper conductive line.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a first lower active contact; a first source/drain pattern on the first lower active contact; a second lower active contact; a second source/drain pattern on the second lower active contact; a lower conductive layer electrically connected to the first and second lower active contacts; a third source/drain pattern and a fourth source/drain pattern between the first and second source/drain patterns; a first upper active contact on the third source/drain pattern; a second upper active contact on the fourth source/drain pattern; and an upper conductive line electrically connected to the first and second upper active contacts, wherein the first to fourth source/drain patterns, the first and second lower active contacts, and the first and second upper active contacts are disposed between the lower conductive layer and upper conductive line.

2 . The semiconductor device of claim 1 , wherein a distance between the first and second upper active contacts is smaller than a distance between the first and second lower active contacts.

3 . The semiconductor device of claim 1 , wherein the lower conductive layer comprises:
a first lower conductive portion overlapped with the first lower active contact; a second lower conductive portion overlapped with the second lower active contact; and a third lower conductive portion connecting the first and second lower conductive portions to each other, wherein the upper conductive line is overlapped with the third lower conductive portion.

4 . The semiconductor device of claim 3 , wherein the upper conductive line is extended in a first direction, and
a length of the third lower conductive portion in the first direction is larger than a length of the first and second lower conductive portions in the first direction.

5 . The semiconductor device of claim 3 , wherein the lower conductive layer further comprises:
a fourth lower conductive portion connected to the third lower conductive portion; and a fifth lower conductive portion connecting the second and fourth lower conductive portions to each other, wherein the third and fifth lower conductive portions are spaced apart from each other, and the second and fourth lower conductive portions are spaced apart from each other.

6 . The semiconductor device of claim 5 , further comprising a lower conductive pattern between the third and fifth lower conductive portions and between the second and fourth lower conductive portions,
wherein the lower conductive layer surrounds the lower conductive pattern.

7 . The semiconductor device of claim 6 , further comprising:
a lower gate contact on the lower conductive pattern; and a gate electrode on the lower gate contact.

8 . A semiconductor device, comprising:
a first source/drain pattern; a first lower active contact in contact with a lower portion of the first source/drain pattern; a second source/drain pattern; a second lower active contact in contact with a lower portion of the second source/drain pattern; a lower conductive layer electrically connected to the first and second lower active contacts; a third source/drain pattern; a first upper active contact in contact with an upper portion of the third source/drain pattern; an upper conductive line electrically connected to the first upper active contact; a fourth source/drain pattern; a second upper active contact in contact with an upper portion of the fourth source/drain pattern; and a first bit line electrically connected to the second upper active contact, wherein the lower conductive layer comprises:
a first lower conductive portion in contact with the first lower active contact;
a second lower conductive portion in contact with the second lower active contact; and
a third lower conductive portion connecting the first and second lower conductive portions to each other,
wherein the first lower conductive portion is overlapped with the first bit line, and the third lower conductive portion is overlapped with the upper conductive line.

9 . The semiconductor device of claim 8 , further comprising a second bit line overlapped with the second lower conductive portion.

10 . The semiconductor device of claim 9 , wherein the upper conductive line is disposed between the first and second bit lines.

11 . The semiconductor device of claim 8 , wherein the first upper active contact is overlapped with the third lower conductive portion.

12 . The semiconductor device of claim 8 , further comprising:
a first gate electrode adjacent to the first source/drain pattern; an upper gate contact in contact with an upper portion of the first gate electrode; a second gate electrode adjacent to the fourth source/drain pattern; and a lower gate contact in contact with a lower portion of the second gate electrode.

13 . The semiconductor device of claim 12 , further comprising:
a lower conductive pattern in contact with a bottom surface of the lower gate contact; and an insulating pattern surrounding the lower conductive pattern, wherein the lower conductive layer surrounds the insulating pattern and the lower conductive pattern.

14 . The semiconductor device of claim 13 , further comprising:
a word line connection pattern in contact with a bottom surface of the lower conductive pattern; and a word line in contact with a bottom surface of the word line connection pattern.

15 . The semiconductor device of claim 8 , wherein the first, second, and fourth source/drain patterns have a first conductivity type, and
the third source/drain pattern has a second conductivity type different from the first conductivity type.

16 . The semiconductor device of claim 8 , further comprising:
a first gate electrode adjacent to the second and third source/drain patterns; a fifth source/drain pattern adjacent to the first gate electrode; and a third lower active contact in contact with a lower portion of the fifth source/drain pattern, wherein the third lower active contact is in contact with the second lower conductive portion.

17 . The semiconductor device of claim 16 , further comprising:
a sixth source/drain pattern, which is adjacent to the fifth source/drain pattern, with the first gate electrode interposed therebetween; a second gate electrode adjacent to the sixth source/drain pattern; and a read word line electrically connected to the second gate electrode.

18 . The semiconductor device of claim 17 , wherein the read word line is disposed at the same level as the first bit line and the upper conductive line.

19 . The semiconductor device of claim 17 , wherein the read word line is disposed at a level lower than the lower conductive layer.

20 . A semiconductor device, comprising:
a first lower insulating layer; a first word line and a second word line provided in the first lower insulating layer and extended in a first direction; a second lower insulating layer on the first lower insulating layer; a first word line connection contact and a second word line connection contact in the second lower insulating layer; a first lower conductive pattern on the first word line connection contact; a second lower conductive pattern on the second word line connection contact; a first insulating pattern surrounding the first lower conductive pattern; a second insulating pattern surrounding the second lower conductive pattern; a lower conductive layer on the second lower insulating layer; a first

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jeewoong
• Lee Kyo-Wook
• Lee Seunghun
• Cho Keun Hwi

Classifications

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/427

  Power or ground buses · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10B10/12 Primary

  comprising a MOSFET load element · CPC title

• Y10S257/903

  FET configuration adapted for use as static memory cell · CPC title